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    <title>topic Machine check error with LD with LDG set in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Machine-check-error-with-LD-with-LDG-set/m-p/804938#M4495</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On a p2041 a machine check exception is raised with LD and LDG bits sets. From the datasheet the errors could be cache parity errors, which to me are CPU silicon faults, or&amp;nbsp;L2MMU multi-way hit or&amp;nbsp;CoreNet Bad Data.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I want to know what can cause the latter two errors. Can someone please explain the two errors?&lt;span class="lia-inline-image-display-wrapper" image-alt="LDandLDGError.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/77963i270FC210E94E492C/image-size/large?v=v2&amp;amp;px=999" role="button" title="LDandLDGError.PNG" alt="LDandLDGError.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 27 Nov 2018 08:03:31 GMT</pubDate>
    <dc:creator>richardvandebun</dc:creator>
    <dc:date>2018-11-27T08:03:31Z</dc:date>
    <item>
      <title>Machine check error with LD with LDG set</title>
      <link>https://community.nxp.com/t5/P-Series/Machine-check-error-with-LD-with-LDG-set/m-p/804938#M4495</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On a p2041 a machine check exception is raised with LD and LDG bits sets. From the datasheet the errors could be cache parity errors, which to me are CPU silicon faults, or&amp;nbsp;L2MMU multi-way hit or&amp;nbsp;CoreNet Bad Data.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I want to know what can cause the latter two errors. Can someone please explain the two errors?&lt;span class="lia-inline-image-display-wrapper" image-alt="LDandLDGError.PNG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/77963i270FC210E94E492C/image-size/large?v=v2&amp;amp;px=999" role="button" title="LDandLDGError.PNG" alt="LDandLDGError.PNG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Nov 2018 08:03:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Machine-check-error-with-LD-with-LDG-set/m-p/804938#M4495</guid>
      <dc:creator>richardvandebun</dc:creator>
      <dc:date>2018-11-27T08:03:31Z</dc:date>
    </item>
    <item>
      <title>Re: Machine check error with LD with LDG set</title>
      <link>https://community.nxp.com/t5/P-Series/Machine-check-error-with-LD-with-LDG-set/m-p/804939#M4496</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;For the "L2MMU multi-way hit" description please refer to the e500mc Core Reference Manual, Table 4-5. Machine Check Exception Sources.&lt;/P&gt;&lt;P&gt;The "CoreNet Bad Data" condition is described after the Table 4-6. Error Report Definitions of the e500mc Core Reference Manual.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Dec 2018 03:55:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Machine-check-error-with-LD-with-LDG-set/m-p/804939#M4496</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-12-17T03:55:51Z</dc:date>
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