<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Adjust the DDR refresh interval in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763912#M4435</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;During normal DDR controller operation it is not required to change its registers values, so the controller behaviour is not specified/guaranteed after a register value is changed when MEM_EN=1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 16 Mar 2018 07:23:35 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2018-03-16T07:23:35Z</dc:date>
    <item>
      <title>Adjust the DDR refresh interval</title>
      <link>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763911#M4434</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can I adjust the register DDR_SDRAM_INTERVAL of P2020 after the MEM_EN bit of the register DDR_SDRAM_CFG has been setted ?&lt;/P&gt;&lt;P&gt;If it can't be&amp;nbsp;realized, how can I adjust the&amp;nbsp;refresh interval when the DDR controller is working ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Mar 2018 02:45:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763911#M4434</guid>
      <dc:creator>ivanzhang</dc:creator>
      <dc:date>2018-03-16T02:45:01Z</dc:date>
    </item>
    <item>
      <title>Re: Adjust the DDR refresh interval</title>
      <link>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763912#M4435</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;During normal DDR controller operation it is not required to change its registers values, so the controller behaviour is not specified/guaranteed after a register value is changed when MEM_EN=1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Mar 2018 07:23:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763912#M4435</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-03-16T07:23:35Z</dc:date>
    </item>
    <item>
      <title>Re: Adjust the DDR refresh interval</title>
      <link>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763913#M4436</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;When Tcase of DDR is over 105℃, I need to change the refresh interval, so how to realize?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 18 Mar 2018 15:56:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763913#M4436</guid>
      <dc:creator>ivanzhang</dc:creator>
      <dc:date>2018-03-18T15:56:46Z</dc:date>
    </item>
    <item>
      <title>Re: Adjust the DDR refresh interval</title>
      <link>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763914#M4437</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Use higher refresh rate from the very beginning.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Mar 2018 02:50:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Adjust-the-DDR-refresh-interval/m-p/763914#M4437</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-03-19T02:50:17Z</dc:date>
    </item>
  </channel>
</rss>

