topic Re: spi protocol sequence in P2040 in P-Series

spi protocol sequence in P2040

gouravjain — Wed, 28 Mar 2018 04:31:59 GMT

Hello All,

Can any one pls let me know about the configuration sequence of SPI protocol initialization in P2040 chipset. Since i want to write FPGA code (slave) which is connected to P2040 chipset on SPI bus.

regards,

Gourav

Re: spi protocol sequence in P2040

ufedor — Wed, 28 Mar 2018 04:53:31 GMT

It is possible to refer to the QorIQ P2040 Reference Manual, 14.6 eSPI programming examples and U-Boot eSPI source code "u-boot/drivers/spi/fsl_espi.c" (u-boot/fsl_espi.c at 503eff00a7119d2690a662ed64e83e4782b7d3d9 · qoriq-open-source/u-boot · GitHub )

Re: spi protocol sequence in P2040

gouravjain — Wed, 28 Mar 2018 09:06:15 GMT

Hi,

Thanks for you reply...

Just went through the section 14.6, and i'm not able to understand how to use SPITF register.

Let's say i want to write 0x10 in slave in that case what would be the value of SPITF register??

Re: spi protocol sequence in P2040

gouravjain — Wed, 28 Mar 2018 09:20:59 GMT

Hi,

In uboot when i do , sf probe 0

i found the below prints, (given some addition prints starting with GJ)

=> sf probe 0
GJ: SPI probed
cs value : 0
gj_temp1 value : 1
GJ: In SPI driver spi_claim_bus
spi_claim_bus: bus:0 cs:0
GJ: CSMODE[0]: 0x28170008
GJ: In SPI driver spi_xfer
GJ: In SPI driver spi_xfer
spi_xfer: slave 0:0 dout 00000000(00000000) din 00000000(00000000) len 6
GJ: In SPI driver spi_cs_activate
GJ: command value 0x5
GJ: event_tx value: 0x208900
***spi_xfer:...9ffa03f4 written
GJ: event_rx value: 0x420ab00
***spi_xfer:...00012018 readed
GJ: event_tx value: 0x208900
***spi_xfer:...18fa03f4 written
GJ: event_rx value: 0x21ecb00
***spi_xfer:...4d010101 readed
SF: Got idcodes
00000000: 01 20 18 4d 01 . .M.
SF: Detected S25FL129P_64K/S25FL128S with page size 64 KiB, total 16 MiB.

Not able to understand the highlighted part.

Re: spi protocol sequence in P2040

gouravjain — Wed, 28 Mar 2018 11:55:27 GMT

Log when i'm trying to write in flash device(slave),

=> sf write 1000000 5 16
GJ: In SPI driver spi_claim_bus
spi_claim_bus: bus:0 cs:0
GJ: CSMODE[0]: 0x28170008
GJ: In SPI driver spi_xfer
spi_xfer: slave 0:0 dout 00000000(00000000) din 00000000(00000000) len 1
GJ: In SPI driver spi_cs_activate
GJ: command value 0x0
GJ: event_tx value: 0x208900
***spi_xfer:...06fa03ec written
GJ: event_rx value: 0x11dcb00
***spi_xfer:...00000000 readed
GJ: In SPI driver spi_xfer
GJ: In SPI driver spi_xfer
spi_xfer: slave 0:0 dout 00000000(00000000) din 00000000(00000000) len 23
GJ: In SPI driver spi_cs_activate
GJ: command value 0x16
GJ: event_tx value: 0x208900
***spi_xfer:...02000005 written
GJ: event_rx value: 0x420ab00
***spi_xfer:...00000000 readed
GJ: event_tx value: 0x208900
***spi_xfer:...02020202 written
GJ: event_rx value: 0x420ab00
***spi_xfer:...00000000 readed
GJ: event_tx value: 0x208900
***spi_xfer:...02010101 written
GJ: event_rx value: 0x420ab00
***spi_xfer:...00000000 readed
GJ: event_tx value: 0x208900
***spi_xfer:...fffffffd written
GJ: event_rx value: 0x420ab00
***spi_xfer:...00000000 readed
GJ: event_tx value: 0x208900
***spi_xfer:...fffffffc written
GJ: event_rx value: 0x420ab00
***spi_xfer:...00000000 readed
GJ: event_tx value: 0x208900
***spi_xfer:...ffffffec written
GJ: event_rx value: 0x31fcb00
***spi_xfer:...00000000 readed
GJ: In SPI driver spi_xfer
GJ: In SPI driver spi_xfer
spi_xfer: slave 0:0 dout 00000000(00000000) din 00000000(00000000) len 2
GJ: In SPI driver spi_cs_activate
GJ: command value 0x1
GJ: event_tx value: 0x208900
***spi_xfer:...05fa03ec written
GJ: event_rx value: 0x21ecb00
***spi_xfer:...00000000 readed
GJ: In SPI driver spi_xfer

As per mu understanding first time SPITF:06fa03ec --> first byte(06) is command for write enable rest didn't get

Second time SPITF:02000005 --> first byte (02) is command for Page Program, rest for address(000005)

Then several times SPITF will hold the transfer data until gets over.

And finally last time SPITF: 05fa03ec --> first byte (05) command byte for read status register and rest bytes didn't understand.

Pls let me know if my understanding is wrong.

Re: spi protocol sequence in P2040

gouravjain — Mon, 02 Apr 2018 03:56:22 GMT

Hi Ufedor,

Waiting for your reply....