topic Re: DDR3 Memory Interface Configuration for U-boot in P-Series https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691717#M4222 <HTML><HEAD></HEAD><BODY><P>Hi Bulat,</P><P></P><P>Thank you for your reply. I have set the DDR_DDR_SDRAM_CFG[x32_EN] = 0 and the DDR_DDR_SDRAM_CFG[DBW] to be 01. Other than this, I will try setting the address to the DDR device as per your suggestion. Is this it, do we need any other configuration change to reflect this in the software (u-boot) part?</P><P>(asking this out of curiosity) In that case how is this value reflected in the u-boot?</P><P>Thanks.</P><P></P><P>Regards,</P><P>Pavankumar</P></BODY></HTML> Fri, 26 May 2017 11:59:41 GMT pavankumarg 2017-05-26T11:59:41Z DDR3 Memory Interface Configuration for U-boot https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691715#M4220 <HTML><HEAD></HEAD><BODY><P>Our board design involves a P1015 processor which is connected to two DDR3 SDRAM chips in 64M*16 (8 bank * 8Mbit * 16). That is the whole 32 bit bus of memory controller in the processor is connected to two 16 bit DDR3 chips. To configure this in u-boot we have&nbsp;made use of DDR_DDR_SDRAM_CFG[x32_EN] bit, which we have cleared as instructed by the definition of that bit. We have correspondingly changed the bit in the p1_p2_rdb_pc.h file in the /include/configs folder in u-boot. Is this it or do we have to make any further changes elsewhere to reflect this configuration.&nbsp;</P><P></P><P>References used were &nbsp;- P1024RM, AN4039</P><P></P><P>Also if possible could you suggest any other references with regard to configuring this part for the&nbsp;u-boot.</P><P></P><P>P.S. - The reference board P1024RDB uses a x8 configuration(of 4 chips) as compared to our board's configuration of x16.</P><P>Thanks.</P></BODY></HTML> Wed, 24 May 2017 06:37:18 GMT https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691715#M4220 pavankumarg 2017-05-24T06:37:18Z Re: DDR3 Memory Interface Configuration for U-boot https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691716#M4221 <HTML><HEAD></HEAD><BODY><P>DDR_DDR_SDRAM_CFG[x32_EN] is not correct option if you use x16 chips to form 32-bit DDR bus. You need to set DDR_DDR_SDRAM_CFG[x32_EN] = 0, and DDR_DDR_SDRAM_CFG[DBW] = 01. In other words you do not need to modify value of the DDR_DDR_SDRAM_CFG register in the p1_p2_rdb_pc.h file. Also you need to set correctly CS0_BNDS register, (0x0000000F in your case) and number of rows in the CS0_CONFIG register.</P><P></P><P>Regards</P><P>Bulat</P></BODY></HTML> Fri, 26 May 2017 11:43:17 GMT https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691716#M4221 Bulat 2017-05-26T11:43:17Z Re: DDR3 Memory Interface Configuration for U-boot https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691717#M4222 <HTML><HEAD></HEAD><BODY><P>Hi Bulat,</P><P></P><P>Thank you for your reply. I have set the DDR_DDR_SDRAM_CFG[x32_EN] = 0 and the DDR_DDR_SDRAM_CFG[DBW] to be 01. Other than this, I will try setting the address to the DDR device as per your suggestion. Is this it, do we need any other configuration change to reflect this in the software (u-boot) part?</P><P>(asking this out of curiosity) In that case how is this value reflected in the u-boot?</P><P>Thanks.</P><P></P><P>Regards,</P><P>Pavankumar</P></BODY></HTML> Fri, 26 May 2017 11:59:41 GMT https://community.nxp.com/t5/P-Series/DDR3-Memory-Interface-Configuration-for-U-boot/m-p/691717#M4222 pavankumarg 2017-05-26T11:59:41Z