Received Packets Not Transferred from FMan Memory to DDR RAM

daniel_will — Mon, 12 Jun 2017 22:56:03 GMT

Hello All,

I am developing bare-metal Ethernet driver software on an XPedite5470 board with the P5020 processor. In this software, I am configuring dTSEC5 for Ethernet Independent mode receive and transmit processing. After dTSEC5, FMan, and the PHY device are initialized, auto-negotiation successfully completes and a link is present as reported by the PHY device. At this point, it appears that the MAC is receiving packets because I see the packets’ data stored in the FMan buffer pool memory, but the data is not transferred to DDR RAM, the Offset In field in the RxQD is not advanced to the next RX buffer descriptor, and the Empty bit is not cleared in the current RX buffer descriptor.

When compared to the dTSEC5/FMan configuration performed by UBoot, where proper dTSEC5 RX port operation was observed (packet data was transferred to DDR RAM with the RxQD and RX BD fields updated correctly), I believe my driver software is correct; however, I have to be missing something. Any help on this matter would be appreciated.

Here are the parameters of my dTSEC5/FMan configuration:

dTSEC5 Registers:

- ECNTRL = 0x00001050

- MACCFG1 = 0x0000000F

- MACCFG2 = 0x00007215

- RCTRL = 0x00000001

- MAXFRM = 0x00000800

BMI Common Registers:

- FMBM_CFG1 = 0x01FF0010

- FMBM_CFG2 = 0x00600018 (reset value)

- FMBM_PP_12 (port parameters for dTSEC5 RX) = 0x03000000

- FMBM_PFS_12 (FIFO parameters for dTSEC5 RX) = 0x0000000F

BMI dTSEC5 RX Registers:

- FMBM_RCFG = 0x81000000

- FMBM_RDA = 0 (reset value)

- FMBM_RFP = 0x03FF03FF (reset value)

- FMBM_RICP = 0x00000002 (reset value)

- FMBM_RIM = 0 (reset value)

- FMBM_REBM = 0x00020000 (reset value)

- FMBM_RFNE = 0x0000000A

- FMBM_RFCA = 0x003C0000

- FMBM_RFPNE = 0x00480000

- FMBM_RFQID = 0x00021200

- FMBM_SPLIODN = 0x0000000E

FMan DMA registers:

- FMDM_MR = 0x10006800

- FMDM_TR = 0x18600060 (reset value)

- FMDM_HY = 0x10400040 (reset value)

- FMDM_PLR6 (for dTSEC5 RX port) = 0x00200020

The following information represents dTSEC5 and FMan status after the reception of several packets.

Parameter RAM dump for the dTSEC5 RX port (note that the CCSR address is 0x0_8000_0000):

0080421200 20000000 00021220 00000000 000B0000

0080421210 00000000 00000000 00000000 00000000

0080421220 00000000 70000100 00800000 00000000 <-- Offset In field not advanced

0080421230 00000000 00000000 00000000 00000000

0080421240 00000000 00000000 00000000 00000000

0080421250 00000000 00000000 00000000 00000000

0080421260 00000000 00000000 00000000 00000000

RX Buffer Descriptor Ring dump for the dTSEC5 RX port:

0070000100 80000000 00000000 00000000 70010200 <-- Empty bit not cleared

0070000110 80000000 00000000 00000000 70010A00

0070000120 80000000 00000000 00000000 70011200

0070000130 80000000 00000000 00000000 70011A00

0070000140 80000000 00000000 00000000 70012200

0070000150 80000000 00000000 00000000 70012A00

0070000160 80000000 00000000 00000000 70013200

0070000170 80000000 00000000 00000000 70013A00

0070000180 08000000 00000000 00000000 00000000

0070000190 00000000 00000000 00000000 00000000

First receive buffer (referenced by first RX BD):

0070010200 00000000 00000000 00000000 00000000 <-- Packet data not transferred from FMan memory

0070010210 00000000 00000000 00000000 00000000

0070010220 00000000 00000000 00000000 00000000

0070010230 00000000 00000000 00000000 00000000

0070010240 00000000 00000000 00000000 00000000

0070010250 00000000 00000000 00000000 00000000

0070010260 00000000 00000000 00000000 00000000

0070010270 00000000 00000000 00000000 00000000

0070010280 00000000 00000000 00000000 00000000

BMI RX registers:

- FMBM_RFRC = 0x00000004 (increments by one after each received packet until the value shown is reached, regardless of the number of received packets)

- FMBM_RBFC = FMBM_RLFC = FMBM_RFFC = FMBM_RFDC = FMBM_RFLDEC = FMBM_RODC = FMBM_RBDC = 0

FMan DMA registers:

- FMDM_SR = 0

- FMDM_TCID = 0

dTSEC5 MIB Counter registers:

- RBYT = 0x00000588

- RPKT = 21

- RCFS = 0

- RMCA = 1

- RBCA = 20

- RXCF = RXPF = RXUO = RALN = RFLR = RCDE = RCSE = RUND = ROVR =RFRG = RJBR = 0

- RDRP = 4

Please let me know if I’ve omitted anything.

Thanks in advance,

Daniel

Re: Received Packets Not Transferred from FMan Memory to DDR RAM

yipingwang — Wed, 21 Jun 2017 08:42:41 GMT

Hello Daniel Will,

Please refer to the attached FMAN driver which I got from NetComm 4.7.

Please refer to ./FM/MAC/dtsec.h and ./FM/Port/fm_port.h.

NetComm is a bare board project driver package, it can be downloaded from from NetComm Software Resources|NXP .

Have a great day,
TIC

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topic Received Packets Not Transferred from FMan Memory to DDR RAM in P-Series

Received Packets Not Transferred from FMan Memory to DDR RAM

Re: Received Packets Not Transferred from FMan Memory to DDR RAM