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    <title>P-SeriesのトピックRe: PCI Express Read Burst Transaction</title>
    <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679574#M4130</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The split size in the described case is equal to the BWC (if BWC is less or equal to negotiated payload size).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 02 Aug 2017 10:13:40 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2017-08-02T10:13:40Z</dc:date>
    <item>
      <title>PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679571#M4127</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Question regarding initiate burst PCI Express transaction from Host CPU .(Using p1022).&lt;/P&gt;&lt;P&gt;As far as I understand CPU access to PCI memory will end-up in a 32bit or 64bit PCIE transfer requests.&lt;/P&gt;&lt;P&gt;Is it possible to create a read transaction of more then 64 bit (that &amp;nbsp;will be implemented in one burst on the PCI Express)?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is it possible to accomplish that with the DMA Controller where source address will point to a PCIE memory space?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Micha&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Jun 2017 05:21:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679571#M4127</guid>
      <dc:creator>michayardeny</dc:creator>
      <dc:date>2017-06-08T05:21:19Z</dc:date>
    </item>
    <item>
      <title>Re: PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679572#M4128</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Your understanding is correct - it is possible to initiate PCIe transfers having data payload more than 64 bytes using DMA.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Jun 2017 05:34:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679572#M4128</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-06-08T05:34:22Z</dc:date>
    </item>
    <item>
      <title>Re: PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679573#M4129</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Basically We have now that DMA working fine with 128 bytes payloads above PCI-E .&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can we theoretically increase DMA transfer size beyond the MPS (Maximum Payload Size)&lt;/P&gt;&lt;P&gt;Or in other works my question is can the&amp;nbsp;host splits DMA transection to smaller TLP packets ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If the answer is negative is that possible to go around it with limiting DMA band width &amp;nbsp;BWC.?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 09:26:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679573#M4129</guid>
      <dc:creator>michayardeny</dc:creator>
      <dc:date>2017-08-02T09:26:10Z</dc:date>
    </item>
    <item>
      <title>Re: PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679574#M4130</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The split size in the described case is equal to the BWC (if BWC is less or equal to negotiated payload size).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 10:13:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679574#M4130</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-08-02T10:13:40Z</dc:date>
    </item>
    <item>
      <title>Re: PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679575#M4131</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks and if BWC is disabled&amp;nbsp;would the DMA split the transaction to maximum payload size TLP's?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 12:28:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679575#M4131</guid>
      <dc:creator>michayardeny</dc:creator>
      <dc:date>2017-08-02T12:28:24Z</dc:date>
    </item>
    <item>
      <title>Re: PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679576#M4132</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Correct.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Aug 2017 12:35:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679576#M4132</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-08-02T12:35:22Z</dc:date>
    </item>
    <item>
      <title>Re: PCI Express Read Burst Transaction</title>
      <link>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679577#M4133</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;@ufedor @Micha_Yardeny&lt;/P&gt;&lt;P&gt;I'm using an LS1012A as an Endpoint and need&amp;nbsp;to read large amounts of data from an RC. Performing memory-mapped reads using the core is working but extremely slow. I assume this is because the MRd TLPs are very small. Can you point me to any code examples showing the use of eDMA with PCIe, or even just a&amp;nbsp;basic overview of how to achieve burst transactions?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Brett S.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 14 Jul 2018 02:04:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/PCI-Express-Read-Burst-Transaction/m-p/679577#M4133</guid>
      <dc:creator>brett_p_stahlma</dc:creator>
      <dc:date>2018-07-14T02:04:06Z</dc:date>
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