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    <title>topic P2020 PHY control problem in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633475#M3765</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;STRONG&gt;P2020 PHY control problem ..&lt;/STRONG&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN&gt;Hello?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;P2020 related questions.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Related to TSEC2 Ethernet PHY chip control&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;MDC, MDIO port measurement result&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;PHY chip control waveform on P2020 (measured by oscilloscope): Normal&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Response waveform on PHY chip: Normal&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;However, output using MII utility commands:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The chip ID value is read as 0000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Even if PHY chip is removed, chip ID value is read as 0000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(Note: TSEC3 Ethernet PHY chip is normally accessed)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;TSEC2, 3 use the same PHY chip&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm curious about the solution.&lt;/SPAN&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;SPAN&gt;Thank you.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 30 Mar 2017 03:28:59 GMT</pubDate>
    <dc:creator>byeongseongjang</dc:creator>
    <dc:date>2017-03-30T03:28:59Z</dc:date>
    <item>
      <title>P2020 PHY control problem</title>
      <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633475#M3765</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;STRONG&gt;P2020 PHY control problem ..&lt;/STRONG&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN&gt;Hello?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;P2020 related questions.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Related to TSEC2 Ethernet PHY chip control&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;MDC, MDIO port measurement result&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;PHY chip control waveform on P2020 (measured by oscilloscope): Normal&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Response waveform on PHY chip: Normal&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;However, output using MII utility commands:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The chip ID value is read as 0000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Even if PHY chip is removed, chip ID value is read as 0000&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;(Note: TSEC3 Ethernet PHY chip is normally accessed)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;TSEC2, 3 use the same PHY chip&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm curious about the solution.&lt;/SPAN&gt;&lt;BR /&gt;&amp;nbsp;&lt;BR /&gt;&lt;SPAN&gt;Thank you.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 03:28:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633475#M3765</guid>
      <dc:creator>byeongseongjang</dc:creator>
      <dc:date>2017-03-30T03:28:59Z</dc:date>
    </item>
    <item>
      <title>Re: P2020 PHY control problem</title>
      <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633476#M3766</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please check value of the eTSEC1 TBI PHY address register (ETSEC1_TBIPA).&lt;/P&gt;&lt;P&gt;Note that MII Management hardware of the eTSEC1 is used to access not only external PHYs,&amp;nbsp; but also internal TBI PHY of the eTSEC1. This is why the TBIPA value must not be equal to any external PHY ID (or you will read internal TBI registers instead of external PHY ones).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 08:55:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633476#M3766</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-03-30T08:55:18Z</dc:date>
    </item>
    <item>
      <title>Re: P2020 PHY control problem</title>
      <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633477#M3767</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN lang="en"&gt;&lt;SPAN&gt;Thank you for the reply.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;TSEC1 is not used.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;The result of checking TBIPA register value is as follows&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;TSEC1 TBIPA = 0x00&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;TSEC2 TBIPA = 0x1F&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;TSEC3 TBIPA = 0x1F&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Is it possible to happen because the values of TSEC2 and TSEC3 are the same?&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN style="display: none;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 10:31:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633477#M3767</guid>
      <dc:creator>byeongseongjang</dc:creator>
      <dc:date>2017-03-30T10:31:29Z</dc:date>
    </item>
    <item>
      <title>Re: P2020 PHY control problem</title>
      <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633478#M3768</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;What are external PHYs addresses?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 15:42:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633478#M3768</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-03-30T15:42:45Z</dc:date>
    </item>
    <item>
      <title>Re: P2020 PHY control problem</title>
      <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633479#M3769</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;External PHYs address&lt;/P&gt;&lt;P&gt;TSEC2 = 00&lt;/P&gt;&lt;P&gt;TSEC3 = 01&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;TSEC2 PHYs address and TSEC1 TBIPA setting value are the same&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Mar 2017 23:57:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633479#M3769</guid>
      <dc:creator>byeongseongjang</dc:creator>
      <dc:date>2017-03-30T23:57:04Z</dc:date>
    </item>
    <item>
      <title>Re: P2020 PHY control problem</title>
      <link>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633480#M3770</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;gt; TSEC2 = 00&lt;/P&gt;&lt;P&gt;Please attentively read my first response and change the eTSEC1 TBIPA to be not equal to 0 and 1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Mar 2017 02:16:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P2020-PHY-control-problem/m-p/633480#M3770</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-03-31T02:16:16Z</dc:date>
    </item>
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