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    <title>topic Re: Regarding P2020 DDR3 write leveling in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Regarding-P2020-DDR3-write-leveling/m-p/613167#M3638</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This could be a complicated issue - please create a Technical Case to investigate it:&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fcommunity.freescale.com%2Fthread%2F381898" rel="nofollow" target="_blank"&gt;https://community.freescale.com/thread/381898&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 08 Feb 2017 06:01:33 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2017-02-08T06:01:33Z</dc:date>
    <item>
      <title>Regarding P2020 DDR3 write leveling</title>
      <link>https://community.nxp.com/t5/P-Series/Regarding-P2020-DDR3-write-leveling/m-p/613166#M3637</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have a board in production using P2020 processors. We had to change to an alternative part for the DDR3 memory as the current one has an EOL. However the new memory part works only when write leveling is disabled.&amp;nbsp; This change in register setting may result in issues when SW update is given to the existing products. Has anyone faced similar issues before&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Feb 2017 05:26:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Regarding-P2020-DDR3-write-leveling/m-p/613166#M3637</guid>
      <dc:creator>vivekvishwanath</dc:creator>
      <dc:date>2017-02-08T05:26:49Z</dc:date>
    </item>
    <item>
      <title>Re: Regarding P2020 DDR3 write leveling</title>
      <link>https://community.nxp.com/t5/P-Series/Regarding-P2020-DDR3-write-leveling/m-p/613167#M3638</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;This could be a complicated issue - please create a Technical Case to investigate it:&lt;/P&gt;&lt;P&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fcommunity.freescale.com%2Fthread%2F381898" rel="nofollow" target="_blank"&gt;https://community.freescale.com/thread/381898&lt;/A&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Feb 2017 06:01:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Regarding-P2020-DDR3-write-leveling/m-p/613167#M3638</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-02-08T06:01:33Z</dc:date>
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