topic Re: P4080 CPC Ecc protection/detection in sram mode in P-Series

P4080 CPC Ecc protection/detection in sram mode

mirkoliebender — Fri, 30 Sep 2016 13:05:39 GMT

Hi, I was wondering if the ecc protection and detection of the P4080s Cpc is also working in sram mode. Error Injection is working fine in Cache mode, but in sram mode no errors are injected. Now I'm wondering if ecc protection and/or detection is actually working in sram mode.

Thanks in advance.

Re: P4080 CPC Ecc protection/detection in sram mode

r8070z — Mon, 17 Oct 2016 06:59:08 GMT

Have a great day,

I had asked expert from the tech support. He said that the ECC is supported but there are errata for injecting errors into the data.

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Re: P4080 CPC Ecc protection/detection in sram mode

mirkoliebender — Mon, 17 Oct 2016 14:02:32 GMT

Hello Serguei,

thank you for your answer. I checked the errata, but the only suitable entry was the one concerning the cpc data injection for less than double-word access. I already got injection working in cache mode for data and tag both, but after putting the cpcs in sram mode neither is working. Do you know anything about that?

Regards, Mirko

Re: P4080 CPC Ecc protection/detection in sram mode

r8070z — Mon, 24 Oct 2016 13:12:02 GMT

I am sorry I tried to find answer but in vain. I asked the design team but the original designer left Freescale some time ago, so no one is sure if ECC would work for SRAM mode. I see that the manual describes only ECC operation in the cache mode too and says not word for the SRAM mode. They asked how did you set up ECC mode for SRAM mode?

Re: P4080 CPC Ecc protection/detection in sram mode

mirkoliebender — Mon, 05 Dec 2016 16:00:51 GMT

Sorry that I didn't answer any time sooner. I deactivated the CPC and re-enabled it in SRAM mode with ECC on. You can find the code of the activation process down below if anyone is interested. I know now that ECC protection and injection is not working in SRAM mode since we testet it with high energy protons.

cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

/* Configure the SRAM upper base address */
out_be32(&cpc->cpcsrcr1, CPC_SRCR1_SRBARU(SRAM_BASE_ADDRESS));

/* Read back to sync write */
in_be32(&cpc->cpcsrcr1);

/* Configure the SRAM lower base address, SRAM size and enable SRAM mode */
out_be32(&cpc->cpcsrcr0,
        CPC_SRCR0_SRAMEN | CPC_SRCR0_SRAMSZ_32_WAY 
        | CPC_SRCR0_SRBARL(SRAM_BASE_ADDRESS ));

/* Read back to sync write */
in_be32(&cpc->cpcsrcr0);

/* Set PAR0 to Default */
setbits_be32(&cpc->cpccsr0 + CPC_CSR0_PAR0/4, 0xfffffbff);
/* Read back to sync write */
in_be32(&cpc->cpccsr0 + CPC_CSR0_PAR0/4);

/* Enable the CPC and ECC*/
out_be32(&cpc->cpccsr0, CPC_CSR0_CE & ~CPC_CSR0_PE);

/* Read back to sync write */
while (!(in_be32(&cpc->cpccsr0) & (CPC_CSR0_CE & ~CPC_CSR0_PE)));
                ;

/* Set CPC Hardware debug control register to not use speculatively requests */
out_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);

/* Read back to sync write */
in_be32(&cpc->cpchdbcr0);

/* Clear error detection bits by setting them */
out_be32(&cpc->cpcerrdet, L3_ERROR_MULTI | L3_ERROR_DATA_SINGLE | L3_ERROR_DATA_MULTI | L3_ERROR_TAG_SINGLE | L3_ERROR_TAG_MULTI | L3_ERROR_TAG_MULTIHIT); 

/* Clear error counter */
clrbits_be32(&cpc->cpcerrctl, 0xffffffff); 
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