topic p2020 initialize fail in P-Series https://community.nxp.com/t5/P-Series/p2020-initialize-fail/m-p/566644#M3441 <HTML><HEAD></HEAD><BODY><P>I design a p2020 board. Using CW while run on sram everything is ok. But if run on DDR3, always initialize fail, ccs prompt :error writing registers, ccs last error ELF is not in expect HALT mode. could this be a hardware problem? I connect ddr's RESET pin to GPIO1, and in the init_core.tcl, I added script and made GPIO1 high before enable mem interface, is that OK?</P></BODY></HTML> Wed, 13 Jul 2016 02:53:48 GMT liuguochen 2016-07-13T02:53:48Z p2020 initialize fail https://community.nxp.com/t5/P-Series/p2020-initialize-fail/m-p/566644#M3441 <HTML><HEAD></HEAD><BODY><P>I design a p2020 board. Using CW while run on sram everything is ok. But if run on DDR3, always initialize fail, ccs prompt :error writing registers, ccs last error ELF is not in expect HALT mode. could this be a hardware problem? I connect ddr's RESET pin to GPIO1, and in the init_core.tcl, I added script and made GPIO1 high before enable mem interface, is that OK?</P></BODY></HTML> Wed, 13 Jul 2016 02:53:48 GMT https://community.nxp.com/t5/P-Series/p2020-initialize-fail/m-p/566644#M3441 liuguochen 2016-07-13T02:53:48Z Re: p2020 initialize fail https://community.nxp.com/t5/P-Series/p2020-initialize-fail/m-p/566645#M3442 <HTML><HEAD></HEAD><BODY><P>Yes, it looks like DDR3 problems. This can include different&nbsp; failure fources, problems with power supplies (GVDD, VTT, MVREF); mistakes with DDR3 schematics, PCB layout; mistakes in DDR3 initialization sequence. Everything should be checked.</P><P></P><P>"I connect ddr's RESET pin to GPIO1" sounds very doubtful. Note that DDR's RESET works under 1.5V supply, GPIO of the P2020 can output 3.3V level. So potentially DDR can be damaged!</P><P></P><P>Regards,</P><P>Bulat</P></BODY></HTML> Wed, 13 Jul 2016 07:56:25 GMT https://community.nxp.com/t5/P-Series/p2020-initialize-fail/m-p/566645#M3442 Bulat 2016-07-13T07:56:25Z