topic Re: Query regarding P1022 in P-Series

Query regarding P1022

rinkutakkar — Tue, 22 Dec 2015 15:58:03 GMT

We are using processor P1022 in one of our designs . We have selected 16-bit GPCM / 28-bit Address mode. We have connected LAD[0:15] to NOR flash via latch but LAD[16:27] are connected directly to flash . As per the reference manual it seems that in this mode LAD[0:15] drives address and data signals in address and data phase respectively but LAD[16:27] are shown as don't care in data phase. Kindly elaborate what will the state of LAD[16:27] in data phase in 16-bit GPCM / 28-bit Address mode.

Card is in fabrication phase and we have just come to know of this issue.We can not make any further changes now.

Kindly clarify will this setup work??

Re: Query regarding P1022

Pavel — Mon, 28 Dec 2015 06:17:30 GMT

Look at the Figure 13-39 of the P1022 Reference Manual. State of the LAD[16:27] in data phase is not specified.

Have a great day,
Pavel

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Re: Query regarding P1022

rinkutakkar — Mon, 28 Dec 2015 06:26:12 GMT

Hi Pavel,

Thanks for your prompt response.

Yes,we have seen that but unfortunately this mistake was overlooked even during review from

freescale. But since our card is now in fabrication stage this can not be modified.So,can you

please elaborate on the actual value on LAD[16:27] during the data phase.

On Sun, 27 Dec 2015 23:18:26 -0700, Pavel wrote

Pavel Chubakov
replied to the discussion "Query regarding P1022"
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Re: Query regarding P1022

Pavel — Mon, 28 Dec 2015 11:59:57 GMT

During address phase (i.e. when LALE is asserted) LAD[16:31] is exactly mirror of LA[167:31]. Then in the GPCM mode LAD[16:31] keep its state during data phase, hence in this case address latched from LAD[27:31] and provided on LA[16:31] are the same.

Have a great day,
Pavel

Re: Query regarding P1022

rinkutakkar — Tue, 29 Dec 2015 04:24:40 GMT

Hi Pavel,

Thanks for your reply. Just to clarify please confirm the following for PMUXCR[eLBC_DIU] = 10; 16-bit GPCM/ 28-bit Address.

Pin Name Address Phase Data Phase

LAD[0:15] A[4:19] D[0:15]

LAD[16:27] A[20:31] A[20:31]*

*So the design will work properly even without latching the LAD[16:27]

Re: Query regarding P1022

rinkutakkar — Tue, 05 Jan 2016 05:46:33 GMT

Hi Pavel,

Please reply to my previous comment. This is really urgent.

Kindly understand the gravity of situation and revert back at the earliest.

We shall be highly obliged.

Regards

Rinku

Re: Query regarding P1022

Pavel — Wed, 06 Jan 2016 06:19:49 GMT

The Table 3-3 of the P1022 Reference Manual shows that A[20:31] are not defined if the PMUXCR[eLBC_DIU] = 10. Latch is needed for A[20:A31]. See the Figure 7 of the P1022 Design Checklist – AN4343:

https://www.nxp.com/webapp/Download?colCode=AN4343&location=null&fpsp=1&WT_TYPE=Application%20Notes&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&fileExt=.pdf&Parent_nodeId=1251753420968693004700&Parent_pageType=product&Parent_nodeId=1251753420968693004700&Parent_pageType=product&Parent_nodeId=1251753420968693004700&Parent_pageType=product

Have a great day,
Pavel