P-SeriesのトピックP1010: Programming model for flash interface timing

P1010: Programming model for flash interface timing

nobelsharanyanj — Tue, 19 Jan 2016 07:01:12 GMT

Hi,

I am using parallel eeprom(AT28BV256 - 5MHz) connecting IFC_GPCM of P1010(rev. 2.0),

In order to test the peripheral I have configured the IFC_FTIM_GPCMn with the parameters present in the peripheral datasheet.

I have doubt in programming the flash interface timing,

IFC clock: 100MHZ, let say my flash timing parameter is 200ns.

Timer counter value = [{200 x 100} + 1000 - 1] / 1000 = 0x15.

please let me know the steps I followed is right.

Regards

Nobel

Re: P1010: Programming model for flash interface timing

Pavel — Tue, 19 Jan 2016 08:52:10 GMT

Look at the Figure 24 of the P1010 Datasheet. See also the Section 12.3.11 of the P1010 Reference Manual. Change the TRAD_NOR, TACO and TSEQRAD_NOR for the AT28BV256 - 5MHz Flash.

The P1010 Datasheet and Reference Manual are available on the following page:

http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-power-architecture-processors/qoriq-p1010-and-p1014-low-power-communications-processors-with-trust-architecture:P1010?fpsp=1&tab=Documentation_Tab

Have a great day,
Pavel

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Re: P1010: Programming model for flash interface timing

nobelsharanyanj — Tue, 19 Jan 2016 09:29:48 GMT

Hi Pavel,

Why I need to change TRAD_NOR -?, Why NOR ?

Do GPCM support eeprom?

See section 12.7.1.

Regards

Nobel

Re: P1010: Programming model for flash interface timing

Pavel — Wed, 20 Jan 2016 04:32:04 GMT

Look at the Figure 12-2 of the P1010 Reference Manual.

This figure shows that GPCM usually is used for synchronous devices.

The AT28BV256 is asynchronous EEPROM. The AT28BV256 interface is asynchronous NOR Flash interface. For example see the AM28F256:

http://noel.feld.cvut.cz/hw/amd/11560f.pdf

Therefore NOR Flash interface usually is used for similar EEPROM.

Have a great day,
Pavel

Re: P1010: Programming model for flash interface timing

nobelsharanyanj — Wed, 20 Jan 2016 09:25:10 GMT

Hi Pavel,

Thanks, Can you explain the same on ADM_SHIFT please.(section 12.4.1.2)

IFC_AD[0:15] - Bidirectional data bus for NOR flash. which used as both address as well as data line with the help of latch in between it,

In that ADM_SHIFT shift the internal address by omitting lsb 7 bits. is it done only for the alignment cause or is there any other reason behind it?

Does programmer need to worry about this?

How does IFC controller knows whether it need to send data in IFC_AD line and address in IFC_ADDR?

kindly explain the same.

Regards

Nobel

Re: P1010: Programming model for flash interface timing

Pavel — Thu, 21 Jan 2016 06:49:19 GMT

Look at the Figures 12-3 and 12-4 of the P1010 Reference Manual. Draw attention that B31 is LSB and B0 is MSB.

The Figure 12-4 shows using the ADM_SHIFT for aligning internal LSB and external LSB.

Have a great day,
Pavel