<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic P1011: Generating PCIe TLP Packet in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/P1011-Generating-PCIe-TLP-Packet/m-p/486912#M2932</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I wished to use memory write operations to fill a FIFO rather than use DMA will the PCIe controller in the P1011 generate a single TLP transaction with a sixteen byte data field if the write transaction was&amp;nbsp; targeted to a data type defined to be of type 4 x 32 bit.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks Anthony&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 04 Feb 2016 13:01:50 GMT</pubDate>
    <dc:creator>anthonyellis</dc:creator>
    <dc:date>2016-02-04T13:01:50Z</dc:date>
    <item>
      <title>P1011: Generating PCIe TLP Packet</title>
      <link>https://community.nxp.com/t5/P-Series/P1011-Generating-PCIe-TLP-Packet/m-p/486912#M2932</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If I wished to use memory write operations to fill a FIFO rather than use DMA will the PCIe controller in the P1011 generate a single TLP transaction with a sixteen byte data field if the write transaction was&amp;nbsp; targeted to a data type defined to be of type 4 x 32 bit.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks Anthony&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Feb 2016 13:01:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1011-Generating-PCIe-TLP-Packet/m-p/486912#M2932</guid>
      <dc:creator>anthonyellis</dc:creator>
      <dc:date>2016-02-04T13:01:50Z</dc:date>
    </item>
    <item>
      <title>Re: P1011: Generating PCIe TLP Packet</title>
      <link>https://community.nxp.com/t5/P-Series/P1011-Generating-PCIe-TLP-Packet/m-p/486913#M2933</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The request is not clear.&lt;/P&gt;&lt;P&gt;1) You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; memory write operations to fill a FIFO&lt;/P&gt;&lt;P&gt;Which exactly operation is in question?&lt;/P&gt;&lt;P&gt;2) You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; data type defined to be of type 4 x 32 bit&lt;/P&gt;&lt;P&gt;What exactly do you mean?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 04 Feb 2016 13:43:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1011-Generating-PCIe-TLP-Packet/m-p/486913#M2933</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-02-04T13:43:03Z</dc:date>
    </item>
  </channel>
</rss>

