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    <title>topic Re: Query regarding P1022 TSEC GTX clock pin in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Query-regarding-P1022-TSEC-GTX-clock-pin/m-p/468681#M2771</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;TSECn_GTX_CLK125 is the reference clock in RGMII mode. You must provide&lt;/P&gt;&lt;P&gt;this clock to the TSEC that is in RGMII mode. It can be taken from any source&lt;/P&gt;&lt;P&gt;that satisfies the requirements of the chip Hardware Specification. &lt;/P&gt;&lt;P&gt;As of the reference clock to the unused SerDes bank, yes, ground the&lt;/P&gt;&lt;P&gt;inputs.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Platon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 27 Jan 2016 17:48:24 GMT</pubDate>
    <dc:creator>bpe</dc:creator>
    <dc:date>2016-01-27T17:48:24Z</dc:date>
    <item>
      <title>Query regarding P1022 TSEC GTX clock pin</title>
      <link>https://community.nxp.com/t5/P-Series/Query-regarding-P1022-TSEC-GTX-clock-pin/m-p/468680#M2770</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have two question during design with P1022-&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. We are using One TSEC of P1022 in RGMII mode. Should we provide 125MHz clock in TSEC1_GTX_CLK125 pin? What should be it's source - Oscillator or external @PHY recovered clock?&lt;/P&gt;&lt;P&gt;2. We are using serdes1 for on 2xPCIe and one SGMII and serdes2 disabled. We provided 100MHz in SD1_REF_CLK pin and SD2_REF_CLK is grounded. Is the scheme correct or do we need to provide clock in SD2_REF_CLK pins as well?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Jan 2016 11:33:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Query-regarding-P1022-TSEC-GTX-clock-pin/m-p/468680#M2770</guid>
      <dc:creator>prasantahalder</dc:creator>
      <dc:date>2016-01-27T11:33:08Z</dc:date>
    </item>
    <item>
      <title>Re: Query regarding P1022 TSEC GTX clock pin</title>
      <link>https://community.nxp.com/t5/P-Series/Query-regarding-P1022-TSEC-GTX-clock-pin/m-p/468681#M2771</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;TSECn_GTX_CLK125 is the reference clock in RGMII mode. You must provide&lt;/P&gt;&lt;P&gt;this clock to the TSEC that is in RGMII mode. It can be taken from any source&lt;/P&gt;&lt;P&gt;that satisfies the requirements of the chip Hardware Specification. &lt;/P&gt;&lt;P&gt;As of the reference clock to the unused SerDes bank, yes, ground the&lt;/P&gt;&lt;P&gt;inputs.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Platon&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Jan 2016 17:48:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Query-regarding-P1022-TSEC-GTX-clock-pin/m-p/468681#M2771</guid>
      <dc:creator>bpe</dc:creator>
      <dc:date>2016-01-27T17:48:24Z</dc:date>
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