topic Re: Booting from IIC in P-Series

Booting from IIC

ivanbatinic — Mon, 07 Dec 2015 15:51:19 GMT

Regarding the P3041 and T2080 processors, am I correct in understanding did the cores will always begin boot program execution from the local bus, and There Is No Possibility of bootloader program code stored in SPI or IIC FLASH?

In otherwords, the PBL sequencer can only use flashdata for RCW and register initialization data, but not for executable boot loader code; It will always require bootloader code to be stored on the local bus (parallel NOR or NAND FLASH).

Is this correct?

BACKGROUND: We are interested in OPTIONALLY Booting from IIC for manufacturing purposes, without Requiring a boot loader in NOR FLASH on the LB to copy IIC programdata to DDR3.

Re: Booting from IIC

sinanakman — Mon, 07 Dec 2015 16:33:59 GMT

Hi Ivan

I don't have the boards but looking at T2080 RM

you can have RCW[203-211] IFC_MODE set to

NOR, SD, SPI, I2C and NAND.

Take a look at Table 4-14. RCW Field Descriptions

on page 210 for IFC_MODE and list of encodings

in Table 4-8. RCW source encodings on page 198.

There are some restriction for having PBL, RCW_SRC

and BOOT_LOC from different devices but you

should be able to boot from I2C within those

limitations. Also Table 5-6. Starting addresses

on page 245 lists the starting addresses.

Hope this helps.

Regards

Sinan Akman

Re: Booting from IIC

r8070z — Fri, 11 Dec 2015 15:30:32 GMT

Have a great day

The P3041 and T2080 can load reset configuration word (RCW) and pre-boot loader (PBL) instructions from the I2C. But they cannot boot from the I2C. The RCW[BOOT_LOC] defines the initial location that the core fetches from. It can be memory on PCIexpress, SRIO, Memory complex 1 and P3041 eLBC or T2080 IFC (See RCW Field Descriptions in the manuals).

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Re: Booting from IIC

ivanbatinic — Mon, 14 Dec 2015 09:18:26 GMT

Thank you for your input thus far--

I have some conflicting answers, and as such, seek further clarification if possible.

In addition, there has been a suggestion made outside of this forum which is complex, but sounds possible using SPI rather than IIC, in order to provide sufficient storage. The SPI device full boot solution is proposed as follows:

1) RCW is contained within an SPI device followed by PBL blocks

2) The PBL blocks "bit-bang" a bootstrap loader (residing in this same RCW SPI boot device, interleaved within the PBL sequences) into the L3 Cache

3) Bootstrap loader starts executing from the L3 Cache after the PBL sequences pounded the bootstrap code into the L3 Cache

4) This bootstrap loader reads the target boot loader executable code from this same SPI device, and copies it to DRAM

5) Control is transferred to the final boot loader code (DRAM) after the full image is copied to DRAM by the bootstrap loader in L3 Cache

6) The target boot loader code can load an application from other devices, or be the application itself; the choice to boot from this external SPI BOOT FLASH device overrides the on-board BOOT FLASH SPI device, allowing the end-user boot loader/application

A compiler such as GCC may be used to compile bootstrap loader into PBL register sequences. The true boot loader is just serially stored after the bootstrap loading PBL blocks.

The result is a full boot requiring only the SPI BOOT FLASH device and DRAM.

Note that the PBL section of the reference manual(s) state that the start address applies to IIC and SPI interfaces as well. This led me to believe that though these are not random access devices, nonetheless, booting could be done from these devices -- it does not state these interfaces are not available for boot code. It does however state that PBL sequences are used up to time zero, which is the start of executable boot code. So I view this as more than confusing.

Does the above mechanism work?