<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>P-SeriesのトピックRe: P1010 IFC_RB_B usage</title>
    <link>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461763#M2684</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The state of IFC_RB_B is reflected in “Ready busy status for each chip-select (IFC_RB_STAT)”, there is no other use of this signal. The “Ready busy status for each chip-select (IFC_RB_STAT)” could be used according to specific software design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q) Does it mean that IFC_RB_B can't be used to extend the NOR FCM transaction in any way?&lt;/P&gt;&lt;P&gt;A) Yes. It cannot be used to extend the NOR FCM transaction in any way.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 28 Apr 2016 10:48:17 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2016-04-28T10:48:17Z</dc:date>
    <item>
      <title>P1010 IFC_RB_B usage</title>
      <link>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461760#M2681</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to access a peripheral device I have attached to IFC CS3_B on my P1010. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The peripheral drives an active low wait signal when it needs to extend the access.&lt;/P&gt;&lt;P&gt;I have the wait output attached to the IFC_RB_B input, it looks to me like the IFC is ignoring the signal.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I currently have CS3 configured in NOR mode, as in GPCM mode the pin acts in the opposite sense to terminate an access quickly (which I can see occurring).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;P1010RM.pdf Table 12-1 (page 508) suggests that IFC_RB_B input is the "NOR Ready Busy Input"&lt;/P&gt;&lt;P&gt;Am I missing something here?&amp;nbsp; Do I need to enable something to get the Chip select to take note of the signal?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;stu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 20 Apr 2016 15:55:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461760#M2681</guid>
      <dc:creator>stu_carmichael</dc:creator>
      <dc:date>2016-04-20T15:55:23Z</dc:date>
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    <item>
      <title>Re: P1010 IFC_RB_B usage</title>
      <link>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461761#M2682</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please provide values of all IFC registers and digital scope trace(s) showing the IFC transaction with IFC_RB_B.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Apr 2016 01:25:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461761#M2682</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-04-21T01:25:28Z</dc:date>
    </item>
    <item>
      <title>Re: P1010 IFC_RB_B usage</title>
      <link>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461762#M2683</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;CS0 = 16-bit NOR boot flash&lt;/P&gt;&lt;P&gt;CS1 = 16-bit NAND flash&lt;/P&gt;&lt;P&gt;CS2 = unused&lt;/P&gt;&lt;P&gt;CS3 = 8 bit peripheral&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Registers are:&lt;/P&gt;&lt;P&gt;IFC Controller Registers&lt;/P&gt;&lt;P&gt;CSPR0:0xEF000105&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; AMASK0:0xFF000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CSOR0:0x0000E001&lt;/P&gt;&lt;P&gt;IFC_FTIM0:0x10020001&lt;/P&gt;&lt;P&gt;IFC_FTIM1:0x14001400&lt;/P&gt;&lt;P&gt;IFC_FTIM2:0x0118000E&lt;/P&gt;&lt;P&gt;IFC_FTIM3:0x00000000&lt;/P&gt;&lt;P&gt;CSPR1:0xFF800103&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; AMASK1:0xFFFF0000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CSOR1:0x85082105&lt;/P&gt;&lt;P&gt;IFC_FTIM0:0x04050404&lt;/P&gt;&lt;P&gt;IFC_FTIM1:0x011A090A&lt;/P&gt;&lt;P&gt;IFC_FTIM2:0x0120201E&lt;/P&gt;&lt;P&gt;IFC_FTIM3:0x00000000&lt;/P&gt;&lt;P&gt;CSPR2:0x00000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; AMASK2:0x00000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CSOR2:0x0000000C&lt;/P&gt;&lt;P&gt;IFC_FTIM0:0x00000000&lt;/P&gt;&lt;P&gt;IFC_FTIM1:0x00000000&lt;/P&gt;&lt;P&gt;IFC_FTIM2:0x00000000&lt;/P&gt;&lt;P&gt;IFC_FTIM3:0x00000000&lt;/P&gt;&lt;P&gt;CSPR3:0xFFB00081&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; AMASK3:0xFFFF0000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CSOR3:0x01020000&lt;/P&gt;&lt;P&gt;IFC_FTIM0:0x10020401&lt;/P&gt;&lt;P&gt;IFC_FTIM1:0x07001E0E&lt;/P&gt;&lt;P&gt;IFC_FTIM2:0x0610181F&lt;/P&gt;&lt;P&gt;IFC_FTIM3:0x00000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;IFC_CCR: 0x07000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;writing a sequential value:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="IFC_write.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/36226i54BFD6017ED83FFD/image-size/large?v=v2&amp;amp;px=999" role="button" title="IFC_write.JPG" alt="IFC_write.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;reading it back:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="IFC_read.JPG"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/36227iB926852D255818FD/image-size/large?v=v2&amp;amp;px=999" role="button" title="IFC_read.JPG" alt="IFC_read.JPG" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;c755_bus is the lower 8 bits of the IFC_AD bus bit swapped.&lt;/P&gt;&lt;P&gt;I triggered the analyser on WAIT going low. The peripheral drives WAIT off the falling edge of IFC_LCLK @50Mhz&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 21 Apr 2016 13:13:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461762#M2683</guid>
      <dc:creator>stu_carmichael</dc:creator>
      <dc:date>2016-04-21T13:13:52Z</dc:date>
    </item>
    <item>
      <title>Re: P1010 IFC_RB_B usage</title>
      <link>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461763#M2684</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The state of IFC_RB_B is reflected in “Ready busy status for each chip-select (IFC_RB_STAT)”, there is no other use of this signal. The “Ready busy status for each chip-select (IFC_RB_STAT)” could be used according to specific software design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q) Does it mean that IFC_RB_B can't be used to extend the NOR FCM transaction in any way?&lt;/P&gt;&lt;P&gt;A) Yes. It cannot be used to extend the NOR FCM transaction in any way.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 Apr 2016 10:48:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1010-IFC-RB-B-usage/m-p/461763#M2684</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2016-04-28T10:48:17Z</dc:date>
    </item>
  </channel>
</rss>

