<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Injecting error by using CPC error injection low register on p3041 in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453654#M2622</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; CPC is configured for cache.&lt;/P&gt;&lt;P&gt;We enabled error detection of single and multi bit on both ddr and cpc.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 16 Sep 2015 17:12:51 GMT</pubDate>
    <dc:creator>mandalakumar</dc:creator>
    <dc:date>2015-09-16T17:12:51Z</dc:date>
    <item>
      <title>Injecting error by using CPC error injection low register on p3041</title>
      <link>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453652#M2620</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Iam trying to inject an error using CPC error injection low register on p3041.&lt;/P&gt;&lt;P&gt;When i do iam getting errors interrrupts from cpc and also from ddr.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is this the behvaiour ?&lt;/P&gt;&lt;P&gt;Any error on CPC will through an error on DDR also ?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Sep 2015 00:55:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453652#M2620</guid>
      <dc:creator>mandalakumar</dc:creator>
      <dc:date>2015-09-16T00:55:10Z</dc:date>
    </item>
    <item>
      <title>Re: Injecting error by using CPC error injection low register on p3041</title>
      <link>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453653#M2621</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Is CPC configured as SRAM or Cache? How do you observe the error from DDR?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Sep 2015 08:36:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453653#M2621</guid>
      <dc:creator>lunminliang</dc:creator>
      <dc:date>2015-09-16T08:36:55Z</dc:date>
    </item>
    <item>
      <title>Re: Injecting error by using CPC error injection low register on p3041</title>
      <link>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453654#M2622</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt; CPC is configured for cache.&lt;/P&gt;&lt;P&gt;We enabled error detection of single and multi bit on both ddr and cpc.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 16 Sep 2015 17:12:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Injecting-error-by-using-CPC-error-injection-low-register-on/m-p/453654#M2622</guid>
      <dc:creator>mandalakumar</dc:creator>
      <dc:date>2015-09-16T17:12:51Z</dc:date>
    </item>
  </channel>
</rss>

