topic Re: P2020 QorIQ enabling the second core in P-Series

P2020 QorIQ enabling the second core

transporter — Sun, 26 Apr 2015 08:29:02 GMT

P2020 QorIQ eTSEC multiple TxBD ringsHi,

I am working on P2020 QoriIQ.

The system starts on core #0 while the core #1 is turned off.

When I start the second core, it gets Instruction Access Exception.

Is there any steps I should make before enabling the second core?

How should I define the TLB for the second core?

Thanks for help :smileyhappy:

Re: P2020 QorIQ enabling the second core

lunminliang — Fri, 08 May 2015 07:28:46 GMT

Hi Eugene Abramsky,

Assume you are using U-Boot? What's value of register BPTR? When second core start, is boot code ready?

The flow in U-Boot:

1. Prepare boot code in memory;

2. Write BPTR register to setup boot page;

3. Release the second core.

Have a great day,
Lunmin

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Re: P2020 QorIQ enabling the second core

lunminliang — Thu, 14 May 2015 03:14:01 GMT

Hello Eugene Abramsky,

For the question "How should I define the TLB for the second core?"

All TLB mapping is created in kernel and driver, not defined as u-boot, users don't need to care more about it.

Have a great day,
Lunmin