<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Custom P2041 board DDR problem in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442574#M2555</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using a custom P2041 board. We were working with u-boot without a problem for 2 months. Last week with no reason u-boot hangs on DDR initialization. After i debugged i realized that DDR controller initialization passes (D_INIT bit is cleared) but read/write procedures to RAM fails. I mean i can't read the same data i wrote. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I checked my board and observed that P2041 sends constantly DDR reset to RAM modules. I can think source of the problem may be following:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- SDRAM hardware problem&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- P2041 hardware problem&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- DDR controller initialization problem (It was working before)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We are using 5xISSI &lt;SPAN lang="EN-US" style="font-family: Tahoma, sans-serif;"&gt;IS43TR16512A-15HBLI 512Mx16 8Gb DDR3 SDRAM with ECC. If anyone experienced similar problem please help me to determine the source of problem. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN lang="EN-US" style="font-family: Tahoma, sans-serif;"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN lang="EN-US" style="font-family: Tahoma, sans-serif;"&gt;Thanks&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 30 Jun 2015 07:32:38 GMT</pubDate>
    <dc:creator>ayhmi</dc:creator>
    <dc:date>2015-06-30T07:32:38Z</dc:date>
    <item>
      <title>Custom P2041 board DDR problem</title>
      <link>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442574#M2555</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using a custom P2041 board. We were working with u-boot without a problem for 2 months. Last week with no reason u-boot hangs on DDR initialization. After i debugged i realized that DDR controller initialization passes (D_INIT bit is cleared) but read/write procedures to RAM fails. I mean i can't read the same data i wrote. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I checked my board and observed that P2041 sends constantly DDR reset to RAM modules. I can think source of the problem may be following:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- SDRAM hardware problem&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- P2041 hardware problem&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;- DDR controller initialization problem (It was working before)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We are using 5xISSI &lt;SPAN lang="EN-US" style="font-family: Tahoma, sans-serif;"&gt;IS43TR16512A-15HBLI 512Mx16 8Gb DDR3 SDRAM with ECC. If anyone experienced similar problem please help me to determine the source of problem. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN lang="EN-US" style="font-family: Tahoma, sans-serif;"&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;SPAN lang="EN-US" style="font-family: Tahoma, sans-serif;"&gt;Thanks&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 30 Jun 2015 07:32:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442574#M2555</guid>
      <dc:creator>ayhmi</dc:creator>
      <dc:date>2015-06-30T07:32:38Z</dc:date>
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    <item>
      <title>Re: Custom P2041 board DDR problem</title>
      <link>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442575#M2556</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;As far as I know P2041 does not have dedicated "DDR reset" signal. When you observed that P2041 sends constantly DDR reset to RAM modules, which P2041 signal you checked? Or more general, how DDR reset is generated on your board?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 30 Jun 2015 13:09:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442575#M2556</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2015-06-30T13:09:35Z</dc:date>
    </item>
    <item>
      <title>Re: Custom P2041 board DDR problem</title>
      <link>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442576#M2557</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I am sorry i misjudged the situation. Yes you are right Bulat. Hardware signals seem correct. However RAM data changes between 2 memory reads.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Jul 2015 05:34:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Custom-P2041-board-DDR-problem/m-p/442576#M2557</guid>
      <dc:creator>ayhmi</dc:creator>
      <dc:date>2015-07-02T05:34:06Z</dc:date>
    </item>
  </channel>
</rss>

