topic [e500] enabling hardware data cache coherency in Linux in P-Series

[e500] enabling hardware data cache coherency in Linux

aleksander — Mon, 05 Oct 2015 11:55:21 GMT

Hello!

I am trying to enable hardware enforced coherency in P2020 in order to speed up communication between core and eTSEC.

Unfortunately, I cannot find, how to set/clear proper bits in MAS2 register, using standard linux kernel API. Is there any way to do this clean way, or should I just hack my way out?

The only proof that Linux might set those bits is in [2], function, but that doesn't lead me to any generic kernel api function.

[1] http://www.freescale.com/files/32bit/doc/app_note/AN3544.pdf

[2] Linux/arch/powerpc/mm/fsl_booke_mmu.c - Linux Cross Reference - Free Electrons

regards

Aleksander

Re: [e500] enabling hardware data cache coherency in Linux

scottwood — Mon, 05 Oct 2015 21:13:31 GMT

Linux already uses coherent DMA on e500-family chips.

Re: [e500] enabling hardware data cache coherency in Linux

aleksander — Tue, 06 Oct 2015 08:38:22 GMT

Can you show how it's done? I suppose, using functions from <linux/dma-mapping.h> you somehow assures, you set proper MAS2 bits, but I'd like to know where it is done.

thanks

Aleksander

Re: [e500] enabling hardware data cache coherency in Linux

scottwood — Tue, 06 Oct 2015 15:23:33 GMT

MAS2[M] is relevant for SMP (and will be set on SMP kernels), not for DMA coherence on e500v2 (e500mc is another matter). As long the device is generating snoops (e.g. TDSEN/TBDSEN/RDSEN/RBDSEN are set), the DMA will be coherent.