P2020 - SerDes equalization operation

jeffbateman — Mon, 26 Oct 2015 17:24:33 GMT

In the P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012, paragraphs for registers GUTS_SRDSCR0 and GUTS_SRDSCR1 list SerDes Tx equalization settings. But, I'm having a hard time finding info about how the equalization operates. This is for a PCIe application, with a requirement to compensate for channel loss.

* Is it pre-emphasis, where the initial amplitude is increased above the final level set in SRDSCR5[SDTXL0..1] and SRDSCR6[SDTXL2..3]?

* Or is it de-emphasis, where the final amplitude is decreased below the initial level set in SRDSCR5[SDTXL0..1] and SRDSCR6[SDTXL2..3]?

* Or, something else?

* And, for how long does the pre / de-emphasis occur?

The only mention of emphasis or equalization I could find is in the P2020 QorIQ Integrated Processor Hardware Specifications, Rev. 2 manual, Para. 2.20.2 Equalization. But that's in the sRIO section, and is just a general discussion with no specifics relating to QorIQ devices.

Also:

* Is there an option to apply receiver equalization?

* Register GUTS_SRDSCR4 controls idle detection for lanes 2 & 3. Is there also a register for lanes 0 & 1?

(curiously, there is no mention of GUTS_SRDSCR3 in the manual, which may or may not be for those lanes)

Thanks for your help.

P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012

Re: P2020 - SerDes equalization operation

LPP — Tue, 27 Oct 2015 07:24:05 GMT

TXEQn defines de-emphasis.

De-emphasis attenuates the voltage level at the transmitter of all consecutive bits of the same signal state except the first. Full amplitude (defived by SDTXLn) is driven at the transmitter for one bit period of the transition bit.

Have a great day,
Pavel

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P-SeriesのトピックP2020 - SerDes equalization operation

P2020 - SerDes equalization operation

Re: P2020 - SerDes equalization operation