topic QoriQ DDR controller input AC timing in P-Series

QoriQ DDR controller input AC timing

fjullien — Fri, 15 Mar 2013 22:41:05 GMT

Hi,

In the P1020 datasheets, the only AC parameter regarding the input timings is tDISKEW (and tCISKEW which is almost the same).

This parameter gives the amount of skew consumed by the controller between MDQS and MDQ/MECC.

It says this value should be substracted from the total timing budget. However, don't we need the input setup and hold time to

determine the timing budget at the controller input ?

I can't find any information about the timing relationship between MCK and DQS (like tDQSS and tDQSCK on the memory side).

Is this something we don't need to know ? Am I missing something ?

Thanks in advance for your help.

Franck.

lunminliang — Mon, 18 Mar 2013 07:23:25 GMT

I am afraid tCISKEW is the only requirement for DQ/DQS input, setup and hold time are due to DQS to DQ skew.

CPO auto-calibration adjusts the time when the the DDR controller expects DQS preamble from the SDRAM. MCK does not matter.

fjullien — Mon, 18 Mar 2013 09:47:42 GMT

Thank you for those informations.

Franck.