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    <title>P-Series中的主题 How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
    <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386102#M2076</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Currently I am trying to run a program on Core 0 of P4080ds. I would like to restrict the program to only use 1/8 of the L3 cache?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;May I know how could I achieve this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter Zheng&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 15 Mar 2015 06:41:53 GMT</pubDate>
    <dc:creator>peterzheng</dc:creator>
    <dc:date>2015-03-15T06:41:53Z</dc:date>
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      <title>How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
      <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386102#M2076</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Currently I am trying to run a program on Core 0 of P4080ds. I would like to restrict the program to only use 1/8 of the L3 cache?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;May I know how could I achieve this?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter Zheng&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 15 Mar 2015 06:41:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386102#M2076</guid>
      <dc:creator>peterzheng</dc:creator>
      <dc:date>2015-03-15T06:41:53Z</dc:date>
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      <title>Re: How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
      <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386103#M2077</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The allocation or mapping is based on the physical address, and sets-ways-lines, the P4080RM.pdf does not detail information for this part. The basic idea is mapping through physical address to sets-ways-lines. As it's not one to one mapping, the replacement algorithm is used:&lt;/P&gt;&lt;P&gt;Configurable pseudo-least recently used (PLRU), streaming PLRU with aging,streaming PLRU without aging, and first-in/first-out (FIFO) replacement policies with programmable allocation policy and update options.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Lunmin&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2015 10:01:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386103#M2077</guid>
      <dc:creator>lunminliang</dc:creator>
      <dc:date>2015-03-16T10:01:33Z</dc:date>
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    <item>
      <title>Re: How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
      <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386104#M2078</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The CPC can be partitioned by way.&amp;nbsp; If you are using the Embedded Hypervisor (Topaz), as your other questions suggest you are, this can be configured using the allocate-cpc-ways property in the hv config tree on the PMA node.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 16 Mar 2015 23:00:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386104#M2078</guid>
      <dc:creator>scottwood</dc:creator>
      <dc:date>2015-03-16T23:00:45Z</dc:date>
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      <title>Re: How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
      <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386105#M2079</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Scott. After partitioning the CPC, if I would like to do some testing, I am thinking about the following method, is this the right way?&lt;/P&gt;&lt;P&gt;(1) boot up the P4080DS into hypervisor, which has partitioned the CPC&lt;/P&gt;&lt;P&gt;(2) Start a bareboard project on CodeWarrior, for each core of P4080DS, one project was created&lt;/P&gt;&lt;P&gt;(3) Run the bareboard project on P4080DS&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Will the test program follow the partition I created?&lt;/P&gt;&lt;P&gt;If not, how would you suggest to test the partition?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Mar 2015 13:24:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386105#M2079</guid>
      <dc:creator>peterzheng</dc:creator>
      <dc:date>2015-03-18T13:24:24Z</dc:date>
    </item>
    <item>
      <title>Re: How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
      <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386106#M2080</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I don't know if CodeWarrior can create standalone applications that run under the hypervisor -- I suggest starting a new thread with that in the subject to get the attention of someone who might know.&amp;nbsp; Certainly, you wouldn't be using CodeWarrior to actually run the project.&amp;nbsp; The hypervisor has to do that.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Mar 2015 21:31:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386106#M2080</guid>
      <dc:creator>scottwood</dc:creator>
      <dc:date>2015-03-18T21:31:14Z</dc:date>
    </item>
    <item>
      <title>Re: How does the L3 cache mapping to memory in P4080DS, how the address was translated?</title>
      <link>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386107#M2081</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Scott.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I will try to start a new thread on this.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Mar 2015 03:33:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/How-does-the-L3-cache-mapping-to-memory-in-P4080DS-how-the/m-p/386107#M2081</guid>
      <dc:creator>peterzheng</dc:creator>
      <dc:date>2015-03-20T03:33:36Z</dc:date>
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