Setting the External Debug Control Register EDBCR0 (P4080)

clemensreibetan — Tue, 27 Jan 2015 21:05:06 GMT

Hi,

I want to set the EDBCR0[EDM] to 0.

How can I do this?

The manual says (E500MCRM, p.329):

Addressing the debug/expert resources through the memory mapped interface entails driving a base

address for the e500mc core (BASE), a functional group select (GID) and register index for a specific

register. The functional group select determines what class of resource is to be accessed, while the register

index determines which resource within the group to access.

Refer to the SoC reference manual for specifics on accessing the internal memory mapped resources via

the external JTAG interface as well as the Aurora high speed serial interface.

What does this mean? (I am using the code warrior tap if this is important)

I hope you can help me.

Re: Setting the External Debug Control Register EDBCR0 (P4080)

lunminliang — Wed, 28 Jan 2015 02:19:37 GMT

Hi,

We have colleague provide a way for previous customer asking about this, to control the EDM/IDM mode, while under debugger control. Please check below:

Enter the following command in the Debugger Shell view, while in a debug session:
    protocol ccs::config_template <core_chain_pos> 0 <value>
where
<core_chain_pos> is the chain position of the core for which you need to alter the EDM mode, eg 1 for core#0, 2 for core#1 etc
<value> is according to the following table:
/* EDM: External Debug Mode. Default value is 1. Values mean:
    * 0: EDM off when running, off when stepping
    * 1: EDM on when running, on when stepping
    * 2: EDM on when running, off when stepping
    * 3: EDM off when running, on when stepping

Please note changing this mode can break CW debugger's functionality.

Have a great day,
Lunmin

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topic Setting the External Debug Control Register EDBCR0 (P4080) in P-Series

Setting the External Debug Control Register EDBCR0 (P4080)

Re: Setting the External Debug Control Register EDBCR0 (P4080)