topic Re: P1022 - Issue on HRESET while loading Flash in P-Series https://community.nxp.com/t5/P-Series/P1022-Issue-on-HRESET-while-loading-Flash/m-p/377987#M1978 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P></P><P><SPAN style="color: #1f497d;">I have a more hardware related question. In AN4343, the Design Checklist, on page 26, note 7 on Figure 5 says “CKSTP_OUT0,CKSTP_OUT1 are POR muxed with cfg_romloc and may need to be separated.”</SPAN></P><P>I thinks this means the two signals can not be connect together as CKSTP_IN, since they are muxed with cfg_rom_loc to be input during reset. As in Figure 5 of the design checklist, CKSTP_OUT are gated while CKSTP_IN not.</P><P></P><P><SPAN style="color: #1f497d;">So, to come full circle, what we’re trying to do right now is hook up the CKSTP1 signal through an AND gate as per the design checklist, but it requires a pullup resistor because it looks like it’s an open drain output (though I can’t confirm that anywhere) and so I’m trying to balance the value of that pullup between pulling the signal high enough for the AND gate to recognize a logic high, and still have the P1022 recognize the pulldown for POR configuration.</SPAN></P><P>In P1022DS, Actel A3P600-FGG484 FPGA is used for cfg_rom_loc. And CKSTP_OUT is pulled up with 4.7K to OVDD</P><P></P><P><BR />Have a great day,<BR />Lunmin</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Tue, 27 Jan 2015 09:19:36 GMT lunminliang 2015-01-27T09:19:36Z P1022 - Issue on HRESET while loading Flash https://community.nxp.com/t5/P-Series/P1022-Issue-on-HRESET-while-loading-Flash/m-p/377986#M1977 <HTML><HEAD></HEAD><BODY><P><SPAN style="color: #1f497d;">I have a more hardware related question. In AN4343, the Design Checklist, on page 26, note 7 on Figure 5 says “CKSTP_OUT0,CKSTP_OUT1 are POR muxed with cfg_romloc and may need to be separated.”</SPAN></P><P></P><P><SPAN style="color: #1f497d;">Our struggle right now is we have a 4.7k pull down resistor on CKSTP_OUT1 to set the CFG_ROM_LOC during POR. I had left this CKSTP output disconnected from the COP interface and just used the CKSTP0 signal to drive it directly, figuring that the two cores would halt pretty much in sync during reset assertion.</SPAN></P><P></P><P><SPAN style="color: #1f497d;">What appears to be happening though is that core 1 is halting a little slower than core 0, and the Codewarrior TAP is reporting that the device is not halted. However, if we probe the HRESET signal, suddenly it thinks the processor is properly halted and proceeds with trying to load the flash.</SPAN></P><P></P><P><SPAN style="color: #1f497d;">Our only theory right now is the extra capacitance of the probe is slowing the HRESET signal down just enough that the other core is able to get halted in time for it to work.</SPAN></P><P></P><P><SPAN style="color: #1f497d;">So, to come full circle, what we’re trying to do right now is hook up the CKSTP1 signal through an AND gate as per the design checklist, but it requires a pullup resistor because it looks like it’s an open drain output (though I can’t confirm that anywhere) and so I’m trying to balance the value of that pullup between pulling the signal high enough for the AND gate to recognize a logic high, and still have the P1022 recognize the pulldown for POR configuration.</SPAN></P><P></P><P><SPAN style="color: #1f497d;">Does any of that make sense? The quoted text at the very top of the email is really confusing to me right now. I’m not sure at all what “may need to be separated” means in a practical sense.</SPAN></P></BODY></HTML> Mon, 26 Jan 2015 18:22:18 GMT https://community.nxp.com/t5/P-Series/P1022-Issue-on-HRESET-while-loading-Flash/m-p/377986#M1977 adamgarrison 2015-01-26T18:22:18Z Re: P1022 - Issue on HRESET while loading Flash https://community.nxp.com/t5/P-Series/P1022-Issue-on-HRESET-while-loading-Flash/m-p/377987#M1978 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P></P><P><SPAN style="color: #1f497d;">I have a more hardware related question. In AN4343, the Design Checklist, on page 26, note 7 on Figure 5 says “CKSTP_OUT0,CKSTP_OUT1 are POR muxed with cfg_romloc and may need to be separated.”</SPAN></P><P>I thinks this means the two signals can not be connect together as CKSTP_IN, since they are muxed with cfg_rom_loc to be input during reset. As in Figure 5 of the design checklist, CKSTP_OUT are gated while CKSTP_IN not.</P><P></P><P><SPAN style="color: #1f497d;">So, to come full circle, what we’re trying to do right now is hook up the CKSTP1 signal through an AND gate as per the design checklist, but it requires a pullup resistor because it looks like it’s an open drain output (though I can’t confirm that anywhere) and so I’m trying to balance the value of that pullup between pulling the signal high enough for the AND gate to recognize a logic high, and still have the P1022 recognize the pulldown for POR configuration.</SPAN></P><P>In P1022DS, Actel A3P600-FGG484 FPGA is used for cfg_rom_loc. And CKSTP_OUT is pulled up with 4.7K to OVDD</P><P></P><P><BR />Have a great day,<BR />Lunmin</P><P></P><P>-----------------------------------------------------------------------------------------------------------------------<BR />Note: If this post answers your question, please click the Correct Answer button. Thank you!<BR />-----------------------------------------------------------------------------------------------------------------------</P></BODY></HTML> Tue, 27 Jan 2015 09:19:36 GMT https://community.nxp.com/t5/P-Series/P1022-Issue-on-HRESET-while-loading-Flash/m-p/377987#M1978 lunminliang 2015-01-27T09:19:36Z