topic Re: P1011 Custom JTAG config in P-Series

P1011 Custom JTAG config

juhalaukkanen — Thu, 22 Jan 2015 07:50:17 GMT

Hello,

I noticed that there is no template jtag chain for P101x target under Freescale\CodeWarrior PA V10.4.0\PA\PA_Support\Initialization_Files\jtag_chains

I need to create custom JTAG config since P1011 based board doesn't work with default JTAG target P1011.

It just gives "CCS last error: Draco/m HIP8: Core not responding" when doing reset or pause after connect.

The board is recognized properly with idcode.tcl script under Freescale\CodeWarrior PA V10.4.0\PA\ccs\bin

TDO -----

* Device 0 IDCODE: 068E301D Device: FSL P1011/P1012 rev 1.x

TDI -----

So my question is how do I make/generate proper JTAG config file for this target?

Thanks.

Re: P1011 Custom JTAG config

addiyi — Thu, 22 Jan 2015 08:01:09 GMT

jtag_chain files are used for RCW override feature and this is available only for high-end cpu (e500mc, e5500, e6500). P101x is based on low-end cpu (e500v2) and no RCW is used for cpu/board configuration.

Please provide more details about your board. It is a custom board?

Adrian

Re: P1011 Custom JTAG config

juhalaukkanen — Thu, 22 Jan 2015 09:08:20 GMT

Thanks for clearing this out! Now I know it is not about RCW.

Yes it is custom board.

However what causes JTAG connection not to work properly? Connection works with defaults settings really well with P1020 RDB Reference Development Board

Re: P1011 Custom JTAG config

lunminliang — Thu, 22 Jan 2015 09:09:25 GMT

Hi,

You may try this:

PQ38 (0x80000000 1)

Attached also.

Have a great day,
Lunmin

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Re: P1011 Custom JTAG config

juhalaukkanen — Thu, 22 Jan 2015 09:28:44 GMT

CW 10.4 doesn't seem to recognize this target PQ38...

Re: P1011 Custom JTAG config

addiyi — Thu, 22 Jan 2015 11:09:40 GMT

Most probably it is a hardware issue. You should recheck the jtag interface.

Adrian

Re: P1011 Custom JTAG config

juhalaukkanen — Wed, 18 Feb 2015 07:09:30 GMT

Yes, this issue was that I2C boot sequence CRC failed and prevented any communication towards the CPU since it was halted.