P-Series中的主题 Active driven voltage level for VBUSCLMP on P1010

Active driven voltage level for VBUSCLMP on P1010

davef — Tue, 10 Feb 2015 16:23:12 GMT

The P1010 datasheet states that VBUSCLMP is in the 3.3V pin group, but the reference design drives the pin to about 1.3V via a resistor-divided VBUS.

What is the correct voltage to drive this pin to assuming we are using the PHY, but not generating VBUS (internal mPCIE USB interface).

Thanks...

Pavel — Wed, 11 Feb 2015 10:38:57 GMT

The P1010 USB controller uses VBUSCLP input as input for detection VBUS voltage.

The P1010 USB controller hardware provides correct working if voltage on this pin is in range into 0v to 1.37V.

Therefore external voltage divider in Vbus usually is used to reduce the voltage range into 0v to 1.37V (external vbus divider ratio is 0.2626).

Factory recommends using divider with precise 51.1k / 18.2k.

This divider is needed if the P1010 USB PHY is not used.

davef — Wed, 11 Feb 2015 13:51:52 GMT

As I stated above, we aren't generating VBUS, so we can't use that specific voltage divider.

Is there a spec for Vin-low(max) and Vin-high(min) for the VBUSCLMP pin? And what is the absolute max voltage we can drive the pin to?

davef — Thu, 19 Feb 2015 20:03:29 GMT

Bump.

Pavel — Fri, 20 Feb 2015 06:07:39 GMT