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    <title>P-SeriesのトピックRe: P1010RDB based board with NAND MT29F8G08ABABA with errors</title>
    <link>https://community.nxp.com/t5/P-Series/P1010RDB-based-board-with-NAND-MT29F8G08ABABA-with-errors/m-p/358369#M1774</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Double-check that the timings are correct.&amp;nbsp; Maybe try more relaxed timing than you think you need.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can see what was written to NAND (or at least, what you're able to read back) by using the "nand dump" command.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 04 Mar 2015 18:27:50 GMT</pubDate>
    <dc:creator>scottwood</dc:creator>
    <dc:date>2015-03-04T18:27:50Z</dc:date>
    <item>
      <title>P1010RDB based board with NAND MT29F8G08ABABA with errors</title>
      <link>https://community.nxp.com/t5/P-Series/P1010RDB-based-board-with-NAND-MT29F8G08ABABA-with-errors/m-p/358368#M1773</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, I have a custom board based on the P1010RDB-PA using Micron NAND MT29F8G08ABABA.&amp;nbsp; Currenlty we have ported over to SDKv1.7, however these same issues occur with SDKv1.5 as well.&amp;nbsp; With SDKv1.5 I had patched U-Boot to add our chip however adding these changes to SDKv1.7 was not needed for the chip to operate. It appears this issue only occurs with some of the &lt;SPAN style="font-size: 13.3333330154419px;"&gt;MT29F8G08ABABA &lt;/SPAN&gt;NAND chips (we have multiple boards) causing me to belive something is on the edge of working.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;The nand chip is programmed by the U-Boot boot loader with a ~30MB file to a 40MB nand partition starting at offset 0x0D600000 .&amp;nbsp; The process of writing to the chip proceeds until the verify portion.&amp;nbsp; Upon verification of the chip the read of a block will fail.&amp;nbsp;&amp;nbsp; Manually attempting to read that block resulted in an error (-74) so I cannot be sure if the block was ever programmed or not. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;Thanks for any input you may have,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;Matt&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;Example of Failure:&lt;/SPAN&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;
&lt;P&gt;NAND boot... &lt;/P&gt;
&lt;P&gt;Second program loader running in sram...&lt;/P&gt;
&lt;P&gt;Tertiary program loader running in sram...&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;U-Boot 2014.07QorIQ-SDK-V1.7+g659b6a2 (Feb 20 2015 - 11:04:31)&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;CPU:&amp;nbsp;&amp;nbsp; P1010E, Version: 2.0, (0x80f90020)&lt;/P&gt;
&lt;P&gt;Core:&amp;nbsp; e500, Version: 5.2, (0x80212152)&lt;/P&gt;
&lt;P&gt;Clock Configuration:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CPU0:800&amp;nbsp; MHz, &lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; CCB:400&amp;nbsp; MHz,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), IFC:100&amp;nbsp; MHz&lt;/P&gt;
&lt;P&gt;L1:&amp;nbsp;&amp;nbsp;&amp;nbsp; D-cache 32 KiB enabled&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I-cache 32 KiB enabled&lt;/P&gt;
&lt;P&gt;Board: DAXUS 42657-xxx, Boot from NAND&lt;/P&gt;
&lt;P&gt;I2C:&amp;nbsp;&amp;nbsp; ready&lt;/P&gt;
&lt;P&gt;SPI:&amp;nbsp;&amp;nbsp; ready&lt;/P&gt;
&lt;P&gt;DRAM:&amp;nbsp; Detected UDIMM &lt;/P&gt;
&lt;P&gt;1 GiB (DDR3, 32-bit, CL=5, ECC off)&lt;/P&gt;
&lt;P&gt;Now running in RAM - U-Boot at: 3fef0000&lt;/P&gt;
&lt;P&gt;L2:&amp;nbsp;&amp;nbsp;&amp;nbsp; 256 KiB already enabled&lt;/P&gt;
&lt;P&gt;NAND:&amp;nbsp; 1024 MiB&lt;/P&gt;
&lt;P&gt;MMC:&amp;nbsp;&amp;nbsp; FSL_SDHC: 0&lt;/P&gt;
&lt;P&gt;EEPROM: No MAC Address Found&lt;/P&gt;
&lt;P&gt;PCIe1: Root Complex of mini PCIe Slot, no link, regs @ 0xffe0a000&lt;/P&gt;
&lt;P&gt;PCIe1: Bus 00 - 00&lt;/P&gt;
&lt;P&gt;PCIe2: Root Complex of PCIe Slot, x1 gen1, regs @ 0xffe09000&lt;/P&gt;
&lt;P&gt;&amp;nbsp; 02:00.0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; - 10ee:0007 - Memory controller&lt;/P&gt;
&lt;P&gt;PCIe2: Bus 01 - 02&lt;/P&gt;
&lt;P&gt;In:&amp;nbsp;&amp;nbsp;&amp;nbsp; serial&lt;/P&gt;
&lt;P&gt;Out:&amp;nbsp;&amp;nbsp; serial&lt;/P&gt;
&lt;P&gt;Err:&amp;nbsp;&amp;nbsp; serial&lt;/P&gt;
&lt;P&gt;Net:&amp;nbsp;&amp;nbsp; eTSEC1 [PRIME]&lt;/P&gt;
&lt;P&gt;Hit any key to stop autoboot:&amp;nbsp; 0 &lt;/P&gt;
&lt;P&gt;=&amp;gt; &lt;/P&gt;
&lt;P&gt;=&amp;gt; run update_system_usb &lt;/P&gt;
&lt;P&gt;(Re)start USB...&lt;/P&gt;
&lt;P&gt;USB0:&amp;nbsp;&amp;nbsp; USB EHCI 1.00&lt;/P&gt;
&lt;P&gt;scanning bus 0 for devices... 2 USB Device(s) found&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; scanning usb for storage devices... 1 Storage Device(s) found&lt;/P&gt;
&lt;P&gt;reading /amadx/uImage.dtb&lt;/P&gt;
&lt;P&gt;23395 bytes read in 35 ms (652.3 KiB/s)&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;NAND erase: device 0 offset 0xca00000, size 0x200000&lt;/P&gt;
&lt;P&gt;Erasing at 0xcb80000 -- 100% complete.&lt;/P&gt;
&lt;P&gt;OK&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;NAND write: device 0 offset 0xca00000, size 0x5b63&lt;/P&gt;
&lt;P&gt;23395 bytes written: OK&lt;/P&gt;
&lt;P&gt;reading /amadx/rootfs.ext2.gz.u-boot&lt;/P&gt;
&lt;P&gt;23403522 bytes read in 1050 ms (21.3 MiB/s)&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;NAND erase: device 0 offset 0xd600000, size 0x2800000&lt;/P&gt;
&lt;P&gt;Erasing at 0xfd80000 -- 100% complete.&lt;/P&gt;
&lt;P&gt;OK&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;&lt;/P&gt;
&lt;P&gt;NAND write: device 0 offset 0xd600000, size 0x1651c02&lt;/P&gt;
&lt;P&gt;NAND write to offset d600000 failed -5&lt;/P&gt;
&lt;P&gt; 0 bytes written: ERROR&lt;/P&gt;
&lt;P&gt;=&amp;gt; &lt;/P&gt;
&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;Current NAND Settings used (taken from P1010RDB.h I can provide the whole file if needed)&lt;/SPAN&gt;&lt;/P&gt;&lt;BLOCKQUOTE&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; ....&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* ONFI NAND Flash mode0 Timing Params */&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_FTIM0&amp;nbsp; (FTIM0_NAND_TCCST(0x07)| \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM0_NAND_TWP(0x18)&amp;nbsp;&amp;nbsp; | \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM0_NAND_TWCHT(0x07) | \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM0_NAND_TWH(0x0a))&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_FTIM1&amp;nbsp; (FTIM1_NAND_TADLE(0x32)| \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM1_NAND_TWBE(0x39)&amp;nbsp; | \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM1_NAND_TRR(0x0e)&amp;nbsp;&amp;nbsp; | \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM1_NAND_TRP(0x18))&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_FTIM2&amp;nbsp; (FTIM2_NAND_TRAD(0x0f) | \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM2_NAND_TREH(0x0a)&amp;nbsp; | \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; FTIM2_NAND_TWHRE(0x1e))&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_FTIM3 0x0&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ....&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_ONFI_DETECTION&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_CSOR&amp;nbsp;&amp;nbsp; (CSOR_NAND_ECC_ENC_EN&amp;nbsp;&amp;nbsp; /* ECC on encode */ \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; | CSOR_NAND_ECC_DEC_EN&amp;nbsp; /* ECC on decode */ \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; | CSOR_NAND_ECC_MODE_4&amp;nbsp; /* 4-bit ECC */ \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; | CSOR_NAND_RAL_3&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* RAL = 3Byes */ \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; | CSOR_NAND_PGS_4K&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Page Size = 4K */ \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; | CSOR_NAND_SPRZ_224&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Spare size = 224 */ \&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; | CSOR_NAND_PB(128))&amp;nbsp; /*Pages Per Block = 128 */&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN style="font-size: 10pt;"&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; #define CONFIG_SYS_NAND_BLOCK_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (512 * 1024)&lt;/SPAN&gt;&lt;/P&gt;
&lt;/BLOCKQUOTE&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Mar 2015 16:24:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1010RDB-based-board-with-NAND-MT29F8G08ABABA-with-errors/m-p/358368#M1773</guid>
      <dc:creator>yensid</dc:creator>
      <dc:date>2015-03-04T16:24:25Z</dc:date>
    </item>
    <item>
      <title>Re: P1010RDB based board with NAND MT29F8G08ABABA with errors</title>
      <link>https://community.nxp.com/t5/P-Series/P1010RDB-based-board-with-NAND-MT29F8G08ABABA-with-errors/m-p/358369#M1774</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Double-check that the timings are correct.&amp;nbsp; Maybe try more relaxed timing than you think you need.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can see what was written to NAND (or at least, what you're able to read back) by using the "nand dump" command.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Mar 2015 18:27:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/P1010RDB-based-board-with-NAND-MT29F8G08ABABA-with-errors/m-p/358369#M1774</guid>
      <dc:creator>scottwood</dc:creator>
      <dc:date>2015-03-04T18:27:50Z</dc:date>
    </item>
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