topic PLL lock on P1020 in P-Series https://community.nxp.com/t5/P-Series/PLL-lock-on-P1020/m-p/353887#M1720 <HTML><HEAD></HEAD><BODY><P>Hello!</P><P></P><P>Is there a way we can internally probe (register, etc) if a given clock PLL is locked and working fine on P1020?</P><P></P><P>We are having issues detecting a PCIe device, we believe this is caused by a deviation on the SerDes <SPAN style="font-size: 10pt;">"SD_REF_CLK", this clock is derived from the main processor PLL.</SPAN></P><P><SPAN style="font-size: 10pt;"><BR /></SPAN></P><P><SPAN style="font-size: 10pt;">Thanks!</SPAN></P><P><SPAN style="font-size: 10pt;">Bruno</SPAN></P></BODY></HTML> Thu, 26 Mar 2015 13:02:58 GMT bfac 2015-03-26T13:02:58Z PLL lock on P1020 https://community.nxp.com/t5/P-Series/PLL-lock-on-P1020/m-p/353887#M1720 <HTML><HEAD></HEAD><BODY><P>Hello!</P><P></P><P>Is there a way we can internally probe (register, etc) if a given clock PLL is locked and working fine on P1020?</P><P></P><P>We are having issues detecting a PCIe device, we believe this is caused by a deviation on the SerDes <SPAN style="font-size: 10pt;">"SD_REF_CLK", this clock is derived from the main processor PLL.</SPAN></P><P><SPAN style="font-size: 10pt;"><BR /></SPAN></P><P><SPAN style="font-size: 10pt;">Thanks!</SPAN></P><P><SPAN style="font-size: 10pt;">Bruno</SPAN></P></BODY></HTML> Thu, 26 Mar 2015 13:02:58 GMT https://community.nxp.com/t5/P-Series/PLL-lock-on-P1020/m-p/353887#M1720 bfac 2015-03-26T13:02:58Z Re: PLL lock on P1020 https://community.nxp.com/t5/P-Series/PLL-lock-on-P1020/m-p/353888#M1721 <HTML><HEAD></HEAD><BODY><P><SPAN style="font-size: 10pt;">SD_REF_CLK is input clock, it is not derived from the main processor PLL<BR /></SPAN></P><P><SPAN style="font-size: 10pt;"><BR /></SPAN></P><P><SPAN style="font-size: 10pt;"><BR /></SPAN></P></BODY></HTML> Wed, 01 Apr 2015 18:19:31 GMT https://community.nxp.com/t5/P-Series/PLL-lock-on-P1020/m-p/353888#M1721 alexander_yakov 2015-04-01T18:19:31Z