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    <title>topic POR boot in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220848#M162</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have an interesting problem related to power up boot of a self made P2041 board.&lt;/P&gt;&lt;P&gt;I configured the chip to hard coded RCW that supports 16b NOR Flash (cfg_rcw_src[0:4] = 1_0010).&lt;/P&gt;&lt;P&gt;however, once POR signal is negated no FLASH chip select signal is asserted and the P2041 remains hang.&lt;/P&gt;&lt;P&gt;one can access its registers via JTAG debugger if needed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;any ideas why there's no chip select?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 18 Oct 2012 11:48:21 GMT</pubDate>
    <dc:creator>arichadav</dc:creator>
    <dc:date>2012-10-18T11:48:21Z</dc:date>
    <item>
      <title>POR boot</title>
      <link>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220848#M162</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have an interesting problem related to power up boot of a self made P2041 board.&lt;/P&gt;&lt;P&gt;I configured the chip to hard coded RCW that supports 16b NOR Flash (cfg_rcw_src[0:4] = 1_0010).&lt;/P&gt;&lt;P&gt;however, once POR signal is negated no FLASH chip select signal is asserted and the P2041 remains hang.&lt;/P&gt;&lt;P&gt;one can access its registers via JTAG debugger if needed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;any ideas why there's no chip select?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Oct 2012 11:48:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220848#M162</guid>
      <dc:creator>arichadav</dc:creator>
      <dc:date>2012-10-18T11:48:21Z</dc:date>
    </item>
    <item>
      <title>Re: POR boot</title>
      <link>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220849#M163</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Please check the status of LA[18:22] during POR. These pins must NOT be pulled down during power-on reset, otherwise may cause processor halt and LCS not toggling.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Apr 2013 03:31:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220849#M163</guid>
      <dc:creator>lunminliang</dc:creator>
      <dc:date>2013-04-18T03:31:52Z</dc:date>
    </item>
    <item>
      <title>Re: POR boot</title>
      <link>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220850#M164</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I'm debugging&amp;nbsp; a customer P2041 board.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;There're issues in P2041 boot up stage,&amp;nbsp; following test cases:&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Test case1: cfg_rcw_src[0:4]配置字 01100 (Nor flash 8bits width)， elbc bus output LCLK0 signal at 6.25MHz, elbc cs0 will output four valid chip select signals ( but p2041rdb output eight&amp;nbsp;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;chip select signals&amp;nbsp; under this case)&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN&gt;In test case1 ,because elbc bus output LCLK0 signal at 6.25MHz,&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG style="border: 0px; font-weight: bold;"&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;Does it mean the clock tree for elbc ok?&lt;/STRONG&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Test case2:&amp;nbsp;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;cfg_rcw_src[0:4]配置字 01101 (Nor flash 16bits width)， elbc bus output LCLK0 signal at 6.25MHz, elbc cs0 will output two valid chip select signals ( but p2041rdb output four&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;chip select signals&amp;nbsp; under this case)&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="background-color: #ffffff; border: 0px; font-weight: inherit;"&gt;Test case3:&amp;nbsp;cfg_rcw_src[0:4] 10000 (hardcode rcw)，RESET_REQ_B is always assert high level '1', it seems the cpu is always at reset status,&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG style="border: 0px; font-weight: bold;"&gt;&amp;nbsp;HRESET&amp;nbsp;is always at low&amp;nbsp;level "0", Asleep is at high "1".&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Test case4: cfg_rcw_src[0:4]配置字 00110（SDHC)，&amp;nbsp;dessert PORESET_B,&amp;nbsp;&amp;nbsp;SDHC_CLK and SDHC_CMD will output some signal&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Test case5: cfg_rcw_src[0:4] 00000 (I2C normal), program I2C eeprom with rcw word , after cpu loaded rcw word from eeprom ,&amp;nbsp;&amp;nbsp;&lt;STRONG style="border: 0px; font-weight: bold;"&gt;the HRESET&amp;nbsp;is also at low&amp;nbsp;level "0",&amp;nbsp;Asleep change to&amp;nbsp; high "1" at the end of load I2C eeprom. But&amp;nbsp;MCKE, MCK is always at low "0".&lt;/STRONG&gt;&lt;/SPAN&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;STRONG style="border: 0px;"&gt;The behaviour corresponds to following&amp;nbsp;&amp;nbsp;&amp;nbsp;Some of the I/O drivers are enabled; specifically, those pins associated with any interface potentially usable as the source of RCW data. All of the DDR I/Os become&lt;BR /&gt;enabled at this point (though MCKE, MCK, MODT are enabled from the beginning).&lt;BR /&gt;The ASLEEP signal is also enabled at this point.&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;STRONG style="border: 0px; font-weight: inherit;"&gt;P2040 QorIQ Integrated Multicore Communication Processor Family Reference Manual, &amp;nbsp;&amp;nbsp;4.6.1 Power-on reset sequence&amp;nbsp; &amp;nbsp; &amp;nbsp;stage 8.&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;STRONG style="border: 0px; font-weight: inherit;"&gt;I use the codewarrior tap to debug the on board CPU,&amp;nbsp; create the p2041 ram attached project to connect to the cpu, get the following message: the CPU type is P2041NXN7NNC&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;Starting Power at Probe test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting IR Scan test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting Bypass Scan test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Starting Arbitrary TAP State Move test ...&lt;BR /&gt;Test result: PASSED&lt;/P&gt;&lt;P&gt;Detected JTAG IDCODEs: OK&lt;BR /&gt;Device 0 IDCODE: 0x018E001D&lt;/P&gt;&lt;P&gt;ccs_jtag_unlock&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; ccs_jtag_unlock; ccs_error = 0&lt;BR /&gt;ccs_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; cc = 0&lt;BR /&gt; device_list: (size = 1)&lt;BR /&gt; device[0]:: core_type=p2040(173)&lt;BR /&gt; ccs_config_chain; ccs_error = 0&lt;BR /&gt;ccs_get_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; device_list: (size = 5)&lt;BR /&gt; ccs_get_config_chain; ccs_error = 0&lt;BR /&gt;ccs_get_config_chain&lt;BR /&gt; serverh = 0&lt;BR /&gt; device_list: (size = 5)&lt;BR /&gt; device[0]:: core_type=p2040(173)&lt;BR /&gt; device[1]:: core_type=e500mc core(119)&lt;BR /&gt; device[2]:: core_type=e500mc core(119)&lt;BR /&gt; device[3]:: core_type=e500mc core(119)&lt;BR /&gt; device[4]:: core_type=e500mc core(119)&lt;BR /&gt; ccs_get_config_chain; ccs_error = 0&lt;BR /&gt;ccs_send_message&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; message = 3&lt;BR /&gt; ccs_send_message; ccs_error = 0&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 30000&lt;BR /&gt; count = 1&lt;BR /&gt; size = 8&lt;BR /&gt; value: (size = 8)&lt;BR /&gt; 00000000 FE000000&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_read_memory&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0x92;size:4;address_hi:0x00000000;address_lo:0xfe0e2094]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 00000000&lt;BR /&gt; ccs_read_memory; ccs_error = 0; duration=3 ms&lt;BR /&gt;ccs_write_memory&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:0]&lt;BR /&gt; addr = [space:0x92;size:4;address_hi:0x00000000;address_lo:0xfe0e2094]&lt;BR /&gt; data: (size = 4)&lt;BR /&gt; 0000000F&lt;BR /&gt; ccs_write_memory; ccs_error = 0; duration=2 ms&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 200005&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 80230032&lt;BR /&gt; ccs_read_register; ccs_error = 0; duration=5 ms&lt;/P&gt;&lt;P&gt;Executing Initialization File: D:\Freescale\workspace\CP200_Boot-core00\CFG\P2041RDB_init_core.tcl&lt;BR /&gt;radix x &lt;BR /&gt;cmdwin::eclipse::config hexprefix 0x &lt;BR /&gt;cmdwin::eclipse::config MemIdentifier v &lt;BR /&gt;cmdwin::eclipse::config MemWidth 32 &lt;BR /&gt;cmdwin::eclipse::config MemAccess 32 &lt;BR /&gt;cmdwin::eclipse::config MemSwap off &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM1 = 0x7000000A1C080000FE000000FE000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM1 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM2 = 0x9000000A1C080000E0000000E0000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM2 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM3 = 0xA000000A1C0800008000000080000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM3 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM4 = 0x9000000A1C080000C0000000C0000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM4 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM5 = 0x9000000A1C080000D0000000D0000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM5 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM6 = 0x4000000A1C080000F8000000F8000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM6 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM7 = 0xA00000081C0800000000000000000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM7 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM8 = 0xA00000081C0800004000000040000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM8 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM9 = 0x500000081C080000F4000000F4000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM9 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM10 = 0x5000000A1C080000F4100000F4100001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM10 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM11 = 0x500000081C080000F4200000F4200001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM11 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM12 = 0x5000000A1C080000F4300000F4300001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM12 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM13 = 0x6000000A1C080000F0000000F0000001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM13 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM14 = 0x1000000A1C080000FFDF0000FFDF0001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM14 &lt;BR /&gt;cmdwin::reg regPPCTLB1/L2MMU_CAM16 = 0x5000000A1C080000F8200000F8200001 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: L2MMU_CAM16 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/PIR %d -np &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_read_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 286&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; BA004E00&lt;BR /&gt; ccs_read_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVPR = 0x-733990720000000 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;failed on register write: IVPR &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR0 = 0x00000100 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 400&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000100&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR0 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR1 = 0x00000200 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 401&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000200&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR1 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR2 = 0x00000300 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 402&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000300&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR2 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR3 = 0x00000400 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 403&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000400&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR3 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR4 = 0x00000500 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 404&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000500&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=2 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR4 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR5 = 0x00000600 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 405&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000600&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR5 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR6 = 0x00000700 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 406&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000700&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=2 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR6 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR7 = 0x00000800 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 407&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000800&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR7 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR8 = 0x00000c00 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 408&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000C00&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR8 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR10 = 0x00000900 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 410&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000900&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR10 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR11 = 0x00000f00 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 411&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000F00&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR11 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR12 = 0x00000b00 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 412&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000B00&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR12 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR13 = 0x00001100 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 413&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001100&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=2 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR13 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR14 = 0x00001000 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 414&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001000&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR14 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR15 = 0x00001500 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 415&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001500&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR15 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/IVOR35 = 0x00001900 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 531&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00001900&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=2 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: IVOR35 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/BUCSR = 0x01400201 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 1013&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 01400201&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: BUCSR &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/HID0 = 0x00000080 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 1008&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00000080&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=1 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: HID0 &lt;BR /&gt;cmdwin::reg e500mc Special Purpose Registers/MSR = 0x00002000 &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;BR /&gt;ccs_write_register&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; index = 2034&lt;BR /&gt; count = 1&lt;BR /&gt; size = 4&lt;BR /&gt; value: (size = 4)&lt;BR /&gt; 00002000&lt;BR /&gt; ccs_write_register; ccs_error = 9; duration=2 ms&lt;BR /&gt; Error message: Core not in debug&lt;BR /&gt;failed on register write: MSR &lt;BR /&gt;ccs_stop_core&lt;BR /&gt; coreh = [serverh:0;cc_index:0;chain_pos:1]&lt;BR /&gt; ccs_stop_core; ccs_error = 5&lt;BR /&gt; Error message: Core not responding&lt;/P&gt;&lt;P style="border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="border: 0px; font-weight: inherit;"&gt;Can&amp;nbsp;you give me any suggestion at these conditions?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 11 Jul 2018 01:57:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/POR-boot/m-p/220850#M164</guid>
      <dc:creator>wxwangyan</dc:creator>
      <dc:date>2018-07-11T01:57:49Z</dc:date>
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