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    <title>topic Re: CPC Partition when I using CPC as SRAM P4080 in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327348#M1422</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you plan to use part of the CPC as SRAM and the rest as L3 cache? I am afraid it's shared among cores.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 17 Oct 2014 06:27:25 GMT</pubDate>
    <dc:creator>lunminliang</dc:creator>
    <dc:date>2014-10-17T06:27:25Z</dc:date>
    <item>
      <title>CPC Partition when I using CPC as SRAM P4080</title>
      <link>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327347#M1421</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can I use the registers for&amp;nbsp; Partition allocation of CPC (CPC1_CPCPAR1....) when I am using CPC as SRAM?&amp;nbsp; Is for assign&amp;nbsp; a private space to each core. &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;thanks!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hymalai Bello &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Oct 2014 15:33:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327347#M1421</guid>
      <dc:creator>hymalaibello</dc:creator>
      <dc:date>2014-10-15T15:33:23Z</dc:date>
    </item>
    <item>
      <title>Re: CPC Partition when I using CPC as SRAM P4080</title>
      <link>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327348#M1422</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you plan to use part of the CPC as SRAM and the rest as L3 cache? I am afraid it's shared among cores.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 17 Oct 2014 06:27:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327348#M1422</guid>
      <dc:creator>lunminliang</dc:creator>
      <dc:date>2014-10-17T06:27:25Z</dc:date>
    </item>
    <item>
      <title>Re: CPC Partition when I using CPC as SRAM P4080</title>
      <link>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327349#M1423</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Hymalai,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;This register is used in the case of PAMU is enabled, users could program CPC registers CPCPIRn, CPCPARn and CPCPWRn to restrict allocation for several partitions when PAMU enabled, and this level of configuration is performed by hypervisor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the Soc each core has its own TLB, I think you could configure TLB entries to implement your purpose to allocate a specific partition of CPC as SRAM for each core.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yiping&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Oct 2014 06:53:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327349#M1423</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2014-10-21T06:53:41Z</dc:date>
    </item>
    <item>
      <title>Re: CPC Partition when I using CPC as SRAM P4080</title>
      <link>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327350#M1424</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lunmin,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I also have similar question? If I want to divide the CPC into 8 equal parts, and let each core use 1 part of CPC, how to achieve that? Is it through setting the register?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Peter Zheng&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 13 Mar 2015 09:58:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/CPC-Partition-when-I-using-CPC-as-SRAM-P4080/m-p/327350#M1424</guid>
      <dc:creator>peterzheng</dc:creator>
      <dc:date>2015-03-13T09:58:42Z</dc:date>
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