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    <title>topic Re: Uboot problem on uncustom P2020RDB-PC board in P-Series</title>
    <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322291#M1364</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have the same problem with Hu.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;W&lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;e can boot the uboot on custom p2020rdb-pc board even if we had no spd files in eeprom.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt; (We used default setting for the p2020rdb-pc board to make uboot, and&amp;nbsp; u-boot verison is 2013-10. )&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Now we change DDR3 to &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;SAMSUNG K4B8G1646B(1 GB *4) instead of original chips on p2020rdb-pc. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;We used the same version of uboot(2013.10) and just modify some address value like Hu did. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;When we boot the uboot, the printing msg was just like to Hu's&lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 10pt; line-height: 1.5em;"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Did it mean that uboot have made relevant configurations that match DDR3 on custom p2020rdb-pc, so even without spd files it still can work.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;But when we change the DDR3 chips, the configurations did not match, so it hang there.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Then which files in uboot should I modify that can make my DDR3 work?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Looking forward to your reply.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Min Zhao&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 21 Jun 2014 14:34:18 GMT</pubDate>
    <dc:creator>敏赵</dc:creator>
    <dc:date>2014-06-21T14:34:18Z</dc:date>
    <item>
      <title>Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322288#M1361</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We have an uncustom P2020RDB-PC board.&lt;/P&gt;&lt;P&gt;The differences from our board to custom P2020RDB-PC borad are:&lt;/P&gt;&lt;P&gt;1. we have 4GB DDR3 instead of 1GB DDR3 on custom board;&lt;/P&gt;&lt;P&gt;2. we have 64MB NOR Flash instead of 16MB NOR Flash on custom board.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;And we built a 36-bit uboot and &lt;SPAN style="font-size: 10pt; line-height: 1.5em;"&gt;modified relevant uboot source code, as below:&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;#define CONFIG_SYS_TEXT_BASE 0xeff80000--------&amp;gt;0xfeff80000&lt;BR /&gt;#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc----------&amp;gt;0xfeffffffc&lt;BR /&gt;#define CONFIG_SYS_CCSRBAR 0xffe00000------------&amp;gt;0xffe00000&lt;/P&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD&gt;#define CONFIG_SYS_SDRAM_SIZE_LAW&lt;/TD&gt;&lt;TD&gt;LAW_SIZE_1G-------&amp;gt;LAW_SIZE_4G &lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;#define CONFIG_CHIP_SELECTS_PER_CTRL&lt;/TD&gt;&lt;TD&gt;1--------&amp;gt;2&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD&gt;#define CONFIG_SYS_MAX_FLASH_SECT&lt;/TD&gt;&lt;TD&gt;128------&amp;gt;512&lt;/TD&gt;&lt;TD&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;#define CONFIG_SYS_FLASH_BASE&amp;nbsp; 0xef000000---------&amp;gt;0xec000000&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We flash the uboot to the last 512kbit on NOR Flash, and when we boot the board, uboot printing msg as below:&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;BR /&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;U-Boot 2013.10 (Jun 19 2014 - 17:42:04)&lt;/STRONG&gt;&lt;BR /&gt; &lt;BR /&gt;&lt;STRONG&gt; CPU0:&amp;nbsp; P2020E, Version: 2.1, (0x80ea0021)&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; Core:&amp;nbsp; e500, Version: 5.1, (0x80211051)&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; Clock Configuration:&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; CPU0:1200 MHz, CPU1:1200 MHz, &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; CCB:600&amp;nbsp; MHz,&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; DDR:400&amp;nbsp; MHz (800 MT/s data rate) (Asynchronous), LBC:37.500 MHz&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; L1:&amp;nbsp;&amp;nbsp;&amp;nbsp; D-cache 32 KiB enabled&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; I-cache 32 KiB enabled&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; Board: MYP2020RDB CPLD: V4.1 PCBA: V4.0&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; rom_loc: nor upper bank&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; SD/MMC : 4-bit Mode &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; eSPI : Enabled&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; I2C:&amp;nbsp;&amp;nbsp; ready &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; SPI:&amp;nbsp;&amp;nbsp; ready &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; DRAM:&amp;nbsp; DIMM 0: is not a DDR3 SPD.&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; SPD error on controller 0! Trying fallback to raw timing calculation&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; Detected UDIMM Fixed DDR on board &lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt; 1 GiB (DDR3, 64-bit, CL=6, ECC off)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;BR /&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;And it stuck here, the DDR3 information shown in msg is still 1GB.&lt;/P&gt;&lt;P&gt;Is there any possible reason for this?&lt;/P&gt;&lt;P&gt;Is this a SPD problem or is there anything we missed when we modify the uboot. &lt;/P&gt;&lt;P&gt;We are looking forward to your advise.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Hu&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Jun 2014 14:12:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322288#M1361</guid>
      <dc:creator>huyang</dc:creator>
      <dc:date>2014-06-20T14:12:14Z</dc:date>
    </item>
    <item>
      <title>Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322289#M1362</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes, it's an SPD error as the message says.&amp;nbsp; The "is not a DDR3 SPD" message is printed by ddr_compute_dimm_parameters() in drivers/ddr/fsl/ddr3_dimm_params.c, when finding a memory type other than SPD_MEMTYPE_DDR3.&amp;nbsp; Assuming this actually is DDR3, either the SPD is incorrect, or something is going wrong when reading it.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Jun 2014 17:32:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322289#M1362</guid>
      <dc:creator>scottwood</dc:creator>
      <dc:date>2014-06-20T17:32:20Z</dc:date>
    </item>
    <item>
      <title>Re: Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322290#M1363</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. Now, we don't have a spd in eeprom.&lt;/P&gt;&lt;P&gt;Since is not a custom board, we don't have a spd file that match our DDR3(Our DDR3: 4 chips of K4B8G1646B-MCK0).&lt;/P&gt;&lt;P&gt;Where should we found the spd file, and how can we flash it to the eeprom?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. We used custom P2020RDB-PC board before.&lt;/P&gt;&lt;P&gt;We got same problem there, but we can boot the uboot even we got no spd files in eeprom.&lt;/P&gt;&lt;P&gt;At that time, the printing log as below:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;CPU0: P2020, Version: 2.1, (0x80e20021)&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;Core: E500, Version: 5.1, (0x80211051)&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;Clock Configuration: &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;&amp;nbsp; CPU0:1000 MHz, CPU1:1000 MHz,&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;&amp;nbsp; CCB:500 MHz, &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;&amp;nbsp; DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:50 MHz&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;L1: D-cache 32 kB enabled &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;&amp;nbsp; I-cache 32 kB enabled &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;Board: P2020RDB-PCA CPLD: V4.1 PCBA: V4.0&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;Error reading i2c boot information!&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;I2C: ready &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;SPI: ready &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;&lt;STRONG&gt;DRAM: DDR: failed to read &lt;/STRONG&gt;&lt;STRONG&gt;&lt;SPAN style="background-color: #ffff00;"&gt;SPD&lt;/SPAN&gt; from address 82&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;&lt;STRONG style="background-color: #ffff00;"&gt;SPD&lt;/STRONG&gt;&lt;STRONG&gt; error on controller 0! Trying fallback to raw timing calculation&amp;nbsp; &lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;Detected UDIMM Fixed DDR on board &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;1 GiB (DDR3, 64-bit, CL=5, ECC off) &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;Flash: 16 MiB &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;L2: 512 KB enabled &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-family: arial, helvetica, sans-serif;"&gt;NAND: 32 MiB&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;MMC:&amp;nbsp; FSL_SDHC: 0&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;PCIe1: Root Complex of mini PCIe SLOT, no link, regs @ 0xffe0a000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;PCIe1: Bus 00 - 00&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;PCIe2: Root Complex of PCIe SLOT, x1, regs @ 0xffe09000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;&amp;nbsp; 02:00.0&amp;nbsp;&amp;nbsp;&amp;nbsp; - 1095:3132 - Mass storage controller&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;PCIe2: Bus 01 - 02&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;In:&amp;nbsp;&amp;nbsp;&amp;nbsp; serial&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;Out:&amp;nbsp; serial&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;Err:&amp;nbsp; serial&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;Net:&amp;nbsp; eTSEC2 is in sgmii mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;uploading VSC7385 microcode from ef000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;PHY reset timed out&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="PlainText"&gt;&lt;SPAN style="font-family: arial, helvetica, sans-serif; color: #000000;"&gt;eTSEC1, eTSEC2, eTSEC3&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;Hit any key to stop autoboot:&amp;nbsp; 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;Why the custom board can work without spd files and now we can't?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;We are looking forward to your reply.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #000000; font-size: 10.5pt; font-family: arial, helvetica, sans-serif;"&gt;Hu&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 21 Jun 2014 05:36:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322290#M1363</guid>
      <dc:creator>huyang</dc:creator>
      <dc:date>2014-06-21T05:36:29Z</dc:date>
    </item>
    <item>
      <title>Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322291#M1364</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have the same problem with Hu.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;W&lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;e can boot the uboot on custom p2020rdb-pc board even if we had no spd files in eeprom.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt; (We used default setting for the p2020rdb-pc board to make uboot, and&amp;nbsp; u-boot verison is 2013-10. )&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Now we change DDR3 to &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;SAMSUNG K4B8G1646B(1 GB *4) instead of original chips on p2020rdb-pc. &lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;We used the same version of uboot(2013.10) and just modify some address value like Hu did. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;When we boot the uboot, the printing msg was just like to Hu's&lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&amp;nbsp; &lt;/SPAN&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif; font-size: 10pt; line-height: 1.5em;"&gt; &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Did it mean that uboot have made relevant configurations that match DDR3 on custom p2020rdb-pc, so even without spd files it still can work.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;But when we change the DDR3 chips, the configurations did not match, so it hang there.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Then which files in uboot should I modify that can make my DDR3 work?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;Looking forward to your reply.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Min Zhao&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 21 Jun 2014 14:34:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322291#M1364</guid>
      <dc:creator>敏赵</dc:creator>
      <dc:date>2014-06-21T14:34:18Z</dc:date>
    </item>
    <item>
      <title>Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322292#M1365</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;You need to create one DRAM config file specific for your DRAM. Also, a c file where you can specify its size and initialization routines. Refer to sample dram initialization source file in u-boot code. This initialization must be done from Flash memory before the code jumps to DRAM.&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Adeel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 22 Jun 2014 12:32:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322292#M1365</guid>
      <dc:creator>adeel</dc:creator>
      <dc:date>2014-06-22T12:32:58Z</dc:date>
    </item>
    <item>
      <title>Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322293#M1366</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;On P2020RDB-PC, the on-board EEPROM is used to store SPD data, if case of absence or corrupted SPD, falling back to timing data embedded in the source code will be used, Raw timing data is extracted from DDR ship datasheet, please refer to the source file board/freescale/p1_p2_rdb_pc/ddr.c.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also please refer to "DDR Setup" section in the header file include/configs/p1_p2_rdb_pc.h for some basic configurations adjustment, for example LAW size.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In addition, if there is no SPD on your target, you could disable SPD(CONFIG_DDR_SPD) in p1_p2_rdb_pc.h and use "Default settings for DDR3"(defined in header file) to configure DDR controller instead.&amp;nbsp; You could use QCS tool to assist you to determine these parameters according to your target, QCS can be downloaded from &lt;A href="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=PE_QORIQ_SUITE&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab" title="http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=PE_QORIQ_SUITE&amp;amp;fpsp=1&amp;amp;tab=Design_Tools_Tab"&gt;PE_QORIQ_SUITE: Processor Expert Software: QorIQ Configuration Suite&lt;/A&gt;.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Yiping&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 24 Jun 2014 10:39:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322293#M1366</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2014-06-24T10:39:06Z</dc:date>
    </item>
    <item>
      <title>Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322294#M1367</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yiping,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your reply.&lt;/P&gt;&lt;P&gt;Now, we already got spd files for our new DDR3 chips.&lt;/P&gt;&lt;P&gt;But we can't get into uboot, is there a way that we can flash spd file into EEPROM through Codewarrior? &lt;/P&gt;&lt;P&gt;Looking forward to your reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Hu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 01 Jul 2014 04:44:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322294#M1367</guid>
      <dc:creator>huyang</dc:creator>
      <dc:date>2014-07-01T04:44:53Z</dc:date>
    </item>
    <item>
      <title>Re: Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322295#M1368</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Hu,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;CodeWarrior doesn't provide direct support to flash I2C EEPROM. You could design a CodeWarrior bare board project to write I2C.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I attached a sample source file for you.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In addition, you also could configure DDR raw timing in u-boot, and boot up u-boot, then write SPD with i2c command under u-boot prompt.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If further assistance is needed, please feel free to let me know.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yiping Wang&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Jul 2014 11:22:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322295#M1368</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2014-07-02T11:22:27Z</dc:date>
    </item>
    <item>
      <title>Re: Uboot problem on uncustom P2020RDB-PC board</title>
      <link>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322296#M1369</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;How should I design the project to write I2C?&lt;/P&gt;&lt;P&gt;First, is it same to build a p2020rdb-pc project when build the project for I2C?&lt;/P&gt;&lt;P&gt;Second, should I replace all .h and .c file with you supplied, and delete the .tcl file?&lt;/P&gt;&lt;P&gt;Third, how should I &lt;SPAN style="color: #3d3d3d; font-family: 'Helvetica Neue', Helvetica, Arial, 'Lucida Grande', sans-serif;"&gt;flash I2C EEPROM?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks a lot.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Min Zhao&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 02 Jul 2014 13:15:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/P-Series/Uboot-problem-on-uncustom-P2020RDB-PC-board/m-p/322296#M1369</guid>
      <dc:creator>敏赵</dc:creator>
      <dc:date>2014-07-02T13:15:32Z</dc:date>
    </item>
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