P-SeriesのトピックRe: P2020rdb NOR boot problem

P2020rdb NOR boot problem

敏赵 — Tue, 06 May 2014 10:58:37 GMT

HI,

I am research the uboot source code of P2020rdb. I have a question about the source code.

[Q]

（1）If I want to boot from NOR Flash,where can I modify the start address of VSC2BIN,dtb,uimage,rootfs and uboot in the flash?

（2）Why are they assigned to the following address? Are there any rules？

The default address: ef000000~efffffff NOR

ef000000~eff03ffff VSC2BIN

ef040000~ef07ffff dtb

ef080000~ef3fffff uImage

ef400000~eff7ffff rootfs

efff8000~efffffff uboot

Best Regards.

Min Zhao

Re: P2020rdb NOR boot problem

addiyi — Tue, 06 May 2014 11:10:37 GMT

Please take a look at this link. You will find useful information about hardware/software configuration for P2020rdb board.

Adrian

Re: P2020rdb NOR boot problem

敏赵 — Wed, 07 May 2014 06:21:02 GMT

Hi, Adrian

Thank you for your reply.

But I have another question. If I want a 1G NOR Flash FC0000000~FFFFFFFFF, how should I assign the address in the NOR(Vitesse 7385 Switch Firmware,dtb image,uImage，JFFS2 image and u-boot )?

Best regards

Min Zhao

Re: P2020rdb NOR boot problem

addiyi — Thu, 08 May 2014 07:30:42 GMT

You can set the assign address as you want. The only restriction is uboot witch should be in the last 512K of NOR flash. Also, for vitesse firmware, you should modify the uboot variable (usually this is: vscfw_addr), in uboot console.

Adrian

Re: P2020rdb NOR boot problem

敏赵 — Thu, 08 May 2014 07:46:02 GMT

Hi, Adrian

Thank you for your reply.

I can't find the files in which these addresses are assigned. Do you know the file names in which I can modify the addresses?

Best regards

Min Zhao

Re: P2020rdb NOR boot problem

addiyi — Thu, 08 May 2014 07:58:37 GMT

No file is necessary. You have to flash your images into the flash (uboot in the last 512K, the rest of images just make sure they fit). Then when you boot the linux, you should have a command like below:

bootm $nor_loadaddr $nor_ramdiskaddr $nor_fdtaddr

Adrian

Re: P2020rdb NOR boot problem

yipingwang — Thu, 08 May 2014 09:42:05 GMT

Please refer to the configuration header file in u-boot include/configs/p1_p2_rdb_pc.h.

In the local bus definition section, NOR Flash base address is defined.

#define CONFIG_SYS_FLASH_BASE 0xef000000

U-BOOT reset vector address definition

#define CONFIG_SYS_TEXT_BASE 0xeff80000

#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc

You also need to touch board related files in board/freescale/p1_p2_rdb_pc/, for example MMU TLB configuration for NOR Flash.

VSC microcode address is defined in u-boot environment, please refer to board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c, for example it is defined as "vscfw_addr = 0xef000000".

For uImage, dtb and rootfs filesystem, you could allocate them according to your requirement, it is better to coincide with Kernel device tree.

Have a great day,
Yiping Wang

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Re: P2020rdb NOR boot problem

敏赵 — Fri, 09 May 2014 01:12:06 GMT

My uboot version is 2013.10. I can't find the assignment statement of "vscfw_addr = 0xef000000" in the p1_p2_rdb_pc.c.

I only find the following:

#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
if ((tmp = getenv("vscfw_addr")) != NULL) {
vscfw_addr = simple_strtoul(tmp, NULL, 16);
printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
if (vsc7385_upload_firmware((void *) vscfw_addr,
CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385 microcode.\n");
} else
puts("No address specified for VSC7385 microcode.\n");
#endif

Best regards

Min Zhao

Re: P2020rdb NOR boot problem

yipingwang — Fri, 09 May 2014 03:15:06 GMT

Probably the above statement makes you misunderstood, I mean vscfw_addr is a u-boot environment variable, by default it is set as 0xef000000, you could configure it to other address under u-boot prompt.

=>setenv vscfw_addr <other_address>

Have a great day,
Yiping Wang

Re: P2020rdb NOR boot problem

敏赵 — Fri, 09 May 2014 07:48:54 GMT

The default configuration of P2020 is:DDR 1G. NOR 16M. NAND 1M.

If I want to use 36bit CPU, DDR 4G, NOR 1G, NAND 32M. I have some modification steps：

（1）To modify DDR.

I will difine config_sys_sdram_size_ law law_size_4G in u-boot include/configs/p1_p2_rdb_pc.h

Can it work? Or I need modify other configurations？

（2）To modify NOR

I will difine config_sys_max_flash_ sect 8192 and define config_sys_flash_base=c0000000 in u-boot include/configs/p1_p2_rdb_pc.h

Can it work? Or I need modify other configurations？

（3）What should I do to the NAND

Best regards

Min Zhao

Re: P2020rdb NOR boot problem

yipingwang — Fri, 09 May 2014 10:40:50 GMT

DDR

You need to modify TLB setting in board/freescale/p1_p2_rdb/tlb.c and also need to pay attention to the DDR controller configuration in ddr.c.

For Flash

Except files tlb.c and law.c in board/freescale/p1_p2_rdb/, you also need to pay attention to local bus controller configuration for your flash devices in include/configs/p1_p2_rdb_pc.h.

For base addresses configuration, please refer to the "Memory map" section in the header file.