P-SeriesのトピックRe: Parallel NOR flash booting

Parallel NOR flash booting

sekharbabu — Mon, 12 May 2014 12:55:14 GMT

What changes needed in uboot - p1_p2_rdb.h file to boot from parallel NOR flash?

In my board, i defined LAWs for NOR flash as: size is 128MB, CS0, flash start address 0xf0000000

0xff700C88 0x000F0000 ;LAWBAR4 : @0xF0000000

0xff700C90 0x8040001A ;LAWAR4 : NOR FLASH 128M

At present I am booting my board from SDcard, and programming u-boot.bin file (separately build for NOR) into NOR flash, removing SDcard and powering on. I could not see boot prompt.

I need help on parallel-NOR flash boot configuration settings for P1011 processor in uboot. I am using u-boot2009.11

Re: Parallel NOR flash booting

yipingwang — Fri, 16 May 2014 09:06:29 GMT

First please configure the hardware switch setting on your target board to boot from NOR Flash.

In the file include/configs/P1_P2_RDB.h

please pay attention to the following setting in memory map section.

#define CONFIG_SYS_FLASH_BASE 0xef000000

You also could define variables TEXT_BASE and RESET_VECTOR_ADDRESS in this header file, please refer to these variables definition in board/freescale/p1_p2_rdb/config.mk.

In addition, you also need to modify law.c and tlb.c in board/freescale/p1_p2_rdb to make it suitable for your target.

Re: Parallel NOR flash booting

sekharbabu — Fri, 16 May 2014 16:04:02 GMT

Wang,

Thanks for the reply. Well, I made the changes on TEXT_BASE and RESET_VECTOR_ADDRESS in the header file as 0xe8000000 and 0xf8fffffc respectively. And also i made the changes in law.c & tlb.c accordingly. I biuld the uboot and observed the u-boot.bin file size 217MB. For the RAMBOOT build the u-boot.bin file size comes to 512kB . Looks like something wrong with my configuration. Can you help me, Please?

Please note that my NOR flash size is 128MB, so i have defined flash starting address as 0xe8000000

#define CONFIG_SYS_FLASH_BASE 0xe8000000

Re: Parallel NOR flash booting

JasonWang_TW — Mon, 19 May 2014 02:52:56 GMT

Hi Babu,

I think the RESET_VECTOR_ADDRESS should be set as 0xefff_fffc ,and CONFIG_SYS_FLASH_BASE 0xe8000000 , of course, you need to make law.c & tlb.c accordingly.

Re: Parallel NOR flash booting

sekharbabu — Tue, 27 May 2014 14:14:33 GMT

Hi Jason,

I have done the changes as you suggested on RESET_VECTOR_ADDRESS and CONFIG_SYS_FLASH_BASE. I compliled the uboot, I am getting u-boot.bin file size as 128MB, is this right file size? it suppose to be 512KB.

Re: Parallel NOR flash booting

JasonWang_TW — Wed, 28 May 2014 02:23:26 GMT

Hi Babu,

I didn't try it before, but the size of uboot 128MB is not right, it should be 512KB, no matter what flash size is.

Have you try not modify the CONFIG_SYS_FLASH_BASE and RESET_VECTOR_ADDRESS , means

#define CONFIG_SYS_FLASH_BASE 0xeff800000

#define RESET_VECTOR_ADDRESS 0xeffffffc

My idea is although your flash size is 128MB, the upper address lines (A27 above) are not connected, P2020 start fetching code from 0xffff_fffc, it will have the same mapping with 0xefff_fffc, By doing that, we probably get 512KB uboot size.

Re: Parallel NOR flash booting

yipingwang — Wed, 28 May 2014 09:49:42 GMT

The parameter TEXT_BASE is incorrect either, this should be u-boot start address on flash, if your flash is from 0xe8000000 to 0xefffffff, and u-boot is put at the last section(as P2020RDB design), TEXT_BASE should be 0xeff80000 and RESET_VECTOR_ADDRESS should be 0xeffffffc, the same with P2020RDB.

Have a great day,
Yiping Wang

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Re: Parallel NOR flash booting

sekharbabu — Wed, 28 May 2014 11:10:45 GMT

Hi Jason,

Yes, changed flash base and reset vector address, now the u-boot.bin file size is 512KB. I have programmed u-boot.bin file into the NOR flash location 0xeff80000 using BDI3000. I removed the BDI3000 and put the board in NOR boot mode (CFG_ROM_LOC(0:3) = 1111, but i am not getting the prompt in the console.

I could probe NOR flash chip select (CS0) is toggeling once. By the way i am using P1011 not P2020

Re: Parallel NOR flash booting

sekharbabu — Wed, 28 May 2014 11:23:54 GMT

Wang,

Well, I did the changes again as Flash base 0xe8000000 and text_base 0xeff80000 and reset_vector 0xeffffffc. Programmed the u-boot.bin in the flash location 0xeff80000 but not booting, not getting the prompt.

Re: Parallel NOR flash booting

JasonWang_TW — Wed, 28 May 2014 12:52:25 GMT

Hi Babu,

There is no difference for P1010 (I am guessing its typo, FSL do not have P1011 part) and P2020, the NOR boot mechanism is the same.

There is my fault , there is the typo in my previous reply , it should be :

#define CONFIG_SYS_FLASH_BASE 0xe800_0000 // this is for 128MB flash

#define RESET_VECTOR_ADDRESS 0xefff_fffc

#define CONFIG_SYS_TEXT_BASE 0xeff8_0000

you should observe several toggling of CS with probe , BDI tool also can be used for the debugging, you can see where the uboot code stuck.

Re: Parallel NOR flash booting

sekharbabu — Wed, 28 May 2014 17:58:14 GMT

Hi Jason,

No, CS0 is toggeling only for 16 times. To make the board in NOR flash boot, CFG_ROM_LOC(0:3) should be 1111, any other configuration settings to be considered?

Re: Parallel NOR flash booting

JasonWang_TW — Thu, 29 May 2014 06:27:29 GMT

Hi Babu,

The hardware config pin associated with Boot Location is only CFG_ROM_LOC(0:3) , so your config is correct

Have you changed law.c and tlb.c accordingly ? due to the flash base and size has changed.

Due to you have probe the CS toggeling , means CPU start to fetch code from NOR, but stuck somewhere else in uboot code.you can use debugging tool (such as Codewarrior or the BDI you used ) to see what's going on on your system.

Re: Parallel NOR flash booting

yipingwang — Thu, 29 May 2014 07:04:24 GMT

Please also pay attention to other NOR Flash related configuration parameters in the header file.

For example OR(AM) and BR registers, please check the values of these registers according to P1020RM and your target FLASH.

#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \

BR_PS_16 | BR_V)

#define CONFIG_FLASH_OR_PRELIM 0xff000ff7

#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */

#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */

#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */

Re: Parallel NOR flash booting

sekharbabu — Thu, 29 May 2014 11:10:43 GMT

Yes, all Flash definitions been defined in the header file properly. BR and OR registers are proper as I am see the CS0 toggeling.