topic Re: MPC5777C DSPI Continuous chip select in Other NXP Products

MPC5777C DSPI Continuous chip select

prathapvc — Sat, 03 Oct 2020 13:58:59 GMT

We have configured DSPI_B to communicate with EEPROM as per the following code

void DSPI_B_Init(void)

{
DSPI_B.MCR.R = 0xC0010001;

DSPI_B_CTAR0 = 0x78011004;

DSPI_B.MCR.B.HALT = 0x1;

}

void WriteToEEPROM(void)

{

uint32_t i = 0,Iter = 0,uMastereData = 0,uLastWord = 0;

DSPI_B.MCR.B.HALT = 0x1;

uMastereData = (0x80010000 | 0x1400);

DSPI_B.PUSHR.PUSHR.R = uMastereData;

uMastereData = (0x80010000 | 0xA5A5);
DSPI_B.PUSHR.PUSHR.R = uMastereData;

DSPI_B.MCR.B.HALT = 0x0;

while((DSPI_B.SR.B.TCF == 0))//Wait for Tx complete
{}

}

We have set the CONT(bit 0) to 1 in DSPI_B.PUSHR to keep the PCS signal asserted between transfers but we have observed that PCS is asserted only for 3.20 microseconds
and de-asserted while data transfer is in progress. Please find the attached snapshot

Re: MPC5777C DSPI Continuous chip select

lukaszadrapa — Mon, 05 Oct 2020 06:39:45 GMT

Hi,

I can see that you use chip select 0 which is configured as active low (inactive state is high).

That means the 3.2us pulse is inactive state. Then the chip select is asserted and data are shifted out as expected. You configured MSB first, so the waveform corresponds to value 0x1400.

I can see nothing wrong here.

Regards,

Lukas

Re: MPC5777C DSPI Continuous chip select

prathapvc — Mon, 05 Oct 2020 13:20:19 GMT

hi,

Thank you for your response. So whether PCS bits in DSPI_PUSHR to be set to 0 to configure chip select 0 as active high (inactive state is Low )

Regards,

Prathap V C

Re: MPC5777C DSPI Continuous chip select

lukaszadrapa — Wed, 07 Oct 2020 11:24:45 GMT

Hi Prathap,

PCS field in PUSHR register only says which chip select will be used for transfer.

If you want to select low or high inactive state, see PCSIS field in MCR register.

Regards,

Lukas