<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Other NXP ProductsのトピックRe: LS1088 DPAA2 L2 Switching features</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/LS1088-DPAA2-L2-Switching-features/m-p/1159375#M9466</link>
    <description>&lt;P&gt;The document you quoted doesn't appear to be originated by NXP. Please be aware,&lt;BR /&gt;that commenting documents of this kind is basically beyond the scope of NXP &lt;BR /&gt;Technical Support, especially when there are more than ten points to comment.&lt;BR /&gt;For the reasons mentioned above, only a very brief feedback can be provided:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The minimum throughput within the Ethernet layer shall be 1.5Gbps / 64byte &lt;BR /&gt;packets with 802.1ad tagging being performed.&lt;BR /&gt;Ethernet throughput shall be extensible, i.e. it should be possible to support &lt;BR /&gt;higher throughput with minimal modification to software or network processing &lt;BR /&gt;hardware.&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 switch is implemented in WRIOP which is a shared resource. The switching&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;throughput depends on the configuration and the set of tasks it executes. &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Performance figures for certain usage scenarios may be available through distributors. &lt;BR /&gt;&lt;/EM&gt;&lt;EM&gt;Contact your distributor for available performance and test reproducibility&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;information.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;The minimum frame size shall be 64 bytes&lt;BR /&gt;Jumbo frames, up to 9000 bytes (of payload) shall be supported&lt;BR /&gt;Ethernet runt frames shall be dropped (a runt frame is less than 64 bytes)&lt;BR /&gt;Any broken Ethernet frame (i.e. incomplete, incorrect CRC, etc.) shall also be dropped&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Ethernet latency shall be less than 10ms&lt;BR /&gt;Ethernet latency should be less than 1ms&lt;BR /&gt;Ethernet jitter shall be measured as Packet Delay Variation (PDV), as per ITU-T Recommendation Y.1540, section 6.2&lt;BR /&gt;Ethernet jitter shall be less than TODO – need to specify value&lt;BR /&gt;PDV should also be calculated in accordance with RFC3393&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 L2 Switch latency and jitter are not specified. WRIOP uses both internal &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;(on-chip) and externally connected memory to store frames. Thus, jitter and switching latency &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;depend on the configuration, load level introduced by the rest of the system and memory characteristics.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Shall be transparent to L2CP frames&lt;EM&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;The switch can be configured to pass or forward to the control port frames that&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;have destination MAC addresses reserved for control protocols.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Shal be transparent to IEEE 1588v2 and NTPv4 frames&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 L2 switch does not support time synchronization protocols and handles &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;frames that belong to them as ordinary frames.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;hall support SyncE, this is encapsulated as;&lt;BR /&gt;- ITU-T Rec. G.8261 that defines aspects about the architecture and the wander performance of SyncE networks&lt;BR /&gt;- ITU-T Rec. G.8262 that specifies Synchronous Ethernet clocks for SyncE&lt;BR /&gt;- ITU-T Rec. G.8264 that describes the specification of Ethernet Synchronization Messaging Channel (ESMC)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;There are no specific provisions for SyncE of any kind.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;All management traffic shall be IPv6 with an optional IPv4 interface&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;The switch is controlled and configured by MC, it does not recognize or handle &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;any management traffic.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;The Access Point shall have a MAC table of at least 10k entries&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 L2 switch is not a wireless access point.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;The RT should have a MAC table of at least 4k entries.&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Shall transparently carry:&lt;BR /&gt;- 802.1D (Bridging &amp;amp; Spanning Tree)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;See the note for L2CP above&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;- 802.1Q (VLAN)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported. There are multiple VLAN-related options, See DPAA2UM, Chapter 14&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;- 802.1P (DSCP QOS)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported. DPAA2UM, Section&amp;nbsp; 14.3.27.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;- 802.1ad (QinQ)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;The switch recognizes and handles only the outmost VLAN tags. The rest is treated&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;as data.&lt;/EM&gt;&lt;/P&gt;
&lt;P class="lia-align-left"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-align-left"&gt;Best Regards,&lt;BR /&gt;Platon&lt;/P&gt;
&lt;P class="lia-align-left"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-align-left"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-60px"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 25 Sep 2020 13:04:51 GMT</pubDate>
    <dc:creator>bpe</dc:creator>
    <dc:date>2020-09-25T13:04:51Z</dc:date>
    <item>
      <title>LS1088 DPAA2 L2 Switching features</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1088-DPAA2-L2-Switching-features/m-p/1156365#M9418</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have DPAA2 user manual and I could not able to find the below features. Could you please provide whether LS1088A supports all the below features&lt;/P&gt;&lt;TABLE width="455"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="455"&gt;The minimum throughput within the Ethernet layer shall be 1.5Gbps / 64byte packets with 802.1ad tagging being performed.&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Ethernet throughput shall be extensible, i.e. it should be possible to support higher throughput with minimal modification to software or network processing hardware.&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;The minimum frame size shall be 64 bytes&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Jumbo frames, up to 9000 bytes (of payload) shall be supported&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Ethernet runt frames shall be dropped (a runt frame is less than 64 bytes)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Any broken Ethernet frame (i.e. incomplete, incorrect CRC, etc.) shall also be dropped&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Ethernet latency shall be less than 10ms&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Ethernet latency should be less than 1ms&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Ethernet jitter shall be measured as Packet Delay Variation (PDV), as per ITU-T Recommendation Y.1540, section 6.2&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Ethernet jitter shall be less than TODO – need to specify value&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;PDV should also be calculated in accordance with RFC3393&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Shall support:&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 802.1D (Bridging &amp;amp; Spanning Tree)&lt;BR /&gt;- 802.1Q (VLAN)&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 802.1P (DSCP QOS)&lt;BR /&gt;- 802.1ad (QinQ)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Shall be transparent to L2CP frames&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Shal be transparent to IEEE 1588v2 and NTPv4 frames&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Shall support SyncE, this is encapsulated as;&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ITU-T Rec. G.8261 that defines aspects about the architecture and the wander performance of SyncE networks&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ITU-T Rec. G.8262 that specifies Synchronous Ethernet clocks for SyncE&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ITU-T Rec. G.8264 that describes the specification of Ethernet Synchronization Messaging Channel (ESMC)&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;All management traffic shall be IPv6 with an optional IPv4 interface&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;The Access Point shall have a MAC table of at least 10k entries&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;The RT should have a MAC table of at least 4k entries.&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="455"&gt;Shall transparently carry:&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 802.1D (Bridging &amp;amp; Spanning Tree)&lt;BR /&gt;- 802.1Q (VLAN)&lt;BR /&gt;-&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 802.1P (DSCP QOS)&lt;BR /&gt;- 802.1ad (QinQ)&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 21 Sep 2020 15:54:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1088-DPAA2-L2-Switching-features/m-p/1156365#M9418</guid>
      <dc:creator>Anandsharmi</dc:creator>
      <dc:date>2020-09-21T15:54:37Z</dc:date>
    </item>
    <item>
      <title>Re: LS1088 DPAA2 L2 Switching features</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/LS1088-DPAA2-L2-Switching-features/m-p/1159375#M9466</link>
      <description>&lt;P&gt;The document you quoted doesn't appear to be originated by NXP. Please be aware,&lt;BR /&gt;that commenting documents of this kind is basically beyond the scope of NXP &lt;BR /&gt;Technical Support, especially when there are more than ten points to comment.&lt;BR /&gt;For the reasons mentioned above, only a very brief feedback can be provided:&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The minimum throughput within the Ethernet layer shall be 1.5Gbps / 64byte &lt;BR /&gt;packets with 802.1ad tagging being performed.&lt;BR /&gt;Ethernet throughput shall be extensible, i.e. it should be possible to support &lt;BR /&gt;higher throughput with minimal modification to software or network processing &lt;BR /&gt;hardware.&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 switch is implemented in WRIOP which is a shared resource. The switching&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;throughput depends on the configuration and the set of tasks it executes. &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Performance figures for certain usage scenarios may be available through distributors. &lt;BR /&gt;&lt;/EM&gt;&lt;EM&gt;Contact your distributor for available performance and test reproducibility&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;information.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;The minimum frame size shall be 64 bytes&lt;BR /&gt;Jumbo frames, up to 9000 bytes (of payload) shall be supported&lt;BR /&gt;Ethernet runt frames shall be dropped (a runt frame is less than 64 bytes)&lt;BR /&gt;Any broken Ethernet frame (i.e. incomplete, incorrect CRC, etc.) shall also be dropped&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Ethernet latency shall be less than 10ms&lt;BR /&gt;Ethernet latency should be less than 1ms&lt;BR /&gt;Ethernet jitter shall be measured as Packet Delay Variation (PDV), as per ITU-T Recommendation Y.1540, section 6.2&lt;BR /&gt;Ethernet jitter shall be less than TODO – need to specify value&lt;BR /&gt;PDV should also be calculated in accordance with RFC3393&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 L2 Switch latency and jitter are not specified. WRIOP uses both internal &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;(on-chip) and externally connected memory to store frames. Thus, jitter and switching latency &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;depend on the configuration, load level introduced by the rest of the system and memory characteristics.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Shall be transparent to L2CP frames&lt;EM&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;The switch can be configured to pass or forward to the control port frames that&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;have destination MAC addresses reserved for control protocols.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Shal be transparent to IEEE 1588v2 and NTPv4 frames&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 L2 switch does not support time synchronization protocols and handles &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;frames that belong to them as ordinary frames.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;hall support SyncE, this is encapsulated as;&lt;BR /&gt;- ITU-T Rec. G.8261 that defines aspects about the architecture and the wander performance of SyncE networks&lt;BR /&gt;- ITU-T Rec. G.8262 that specifies Synchronous Ethernet clocks for SyncE&lt;BR /&gt;- ITU-T Rec. G.8264 that describes the specification of Ethernet Synchronization Messaging Channel (ESMC)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;There are no specific provisions for SyncE of any kind.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;All management traffic shall be IPv6 with an optional IPv4 interface&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;The switch is controlled and configured by MC, it does not recognize or handle &lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;any management traffic.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;The Access Point shall have a MAC table of at least 10k entries&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;DPAA2 L2 switch is not a wireless access point.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;The RT should have a MAC table of at least 4k entries.&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;Shall transparently carry:&lt;BR /&gt;- 802.1D (Bridging &amp;amp; Spanning Tree)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;See the note for L2CP above&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;- 802.1Q (VLAN)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported. There are multiple VLAN-related options, See DPAA2UM, Chapter 14&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;&lt;BR /&gt;- 802.1P (DSCP QOS)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;Supported. DPAA2UM, Section&amp;nbsp; 14.3.27.&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;- 802.1ad (QinQ)&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&lt;EM&gt;The switch recognizes and handles only the outmost VLAN tags. The rest is treated&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;as data.&lt;/EM&gt;&lt;/P&gt;
&lt;P class="lia-align-left"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-align-left"&gt;Best Regards,&lt;BR /&gt;Platon&lt;/P&gt;
&lt;P class="lia-align-left"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-align-left"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-30px"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P class="lia-indent-padding-left-60px"&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 25 Sep 2020 13:04:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/LS1088-DPAA2-L2-Switching-features/m-p/1159375#M9466</guid>
      <dc:creator>bpe</dc:creator>
      <dc:date>2020-09-25T13:04:51Z</dc:date>
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  </channel>
</rss>

