<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Other NXP ProductsのトピックSDRAM Address testing</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/SDRAM-Address-testing/m-p/164401#M930</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;Wanted to know the below:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I wanted to know..... How the address given by the processor, say 0xA0000000 is the memory mapped address of the sdram. And the SDRAM is a 32MB which is 16M x16 datalines.&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Now there are 24 address lines used... 13 (A0-A12) for Rows + 9 (A0 -A8) for columns + 2 for Banks (BA0,BA1)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;now if i want to write to the 0xA0008000 location (meaning A15 is high) but there is no A15 address line connected.&lt;/DIV&gt;&lt;DIV&gt;hence i wanted to know which address lines would be high and low for accessing memory location 0xA0008000&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Can someone help me with this?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;2. also wanted to know... How can i test the SDRAM address lines with the help of JTAG.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Awai your reply.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Queen245&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 15 Nov 2007 20:32:13 GMT</pubDate>
    <dc:creator>queen245</dc:creator>
    <dc:date>2007-11-15T20:32:13Z</dc:date>
    <item>
      <title>SDRAM Address testing</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SDRAM-Address-testing/m-p/164401#M930</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV&gt;Hi,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;Wanted to know the below:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;I wanted to know..... How the address given by the processor, say 0xA0000000 is the memory mapped address of the sdram. And the SDRAM is a 32MB which is 16M x16 datalines.&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Now there are 24 address lines used... 13 (A0-A12) for Rows + 9 (A0 -A8) for columns + 2 for Banks (BA0,BA1)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;now if i want to write to the 0xA0008000 location (meaning A15 is high) but there is no A15 address line connected.&lt;/DIV&gt;&lt;DIV&gt;hence i wanted to know which address lines would be high and low for accessing memory location 0xA0008000&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Can someone help me with this?&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;2. also wanted to know... How can i test the SDRAM address lines with the help of JTAG.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Awai your reply.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Queen245&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 15 Nov 2007 20:32:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SDRAM-Address-testing/m-p/164401#M930</guid>
      <dc:creator>queen245</dc:creator>
      <dc:date>2007-11-15T20:32:13Z</dc:date>
    </item>
    <item>
      <title>Re: SDRAM Address testing</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SDRAM-Address-testing/m-p/164402#M931</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;Hi Queen245,&lt;BR /&gt;&lt;BR /&gt;The SDRAM is addressed&amp;nbsp; through column and&amp;nbsp; Row address seperately and it is handled by the SDRAM controller.&amp;nbsp; The Physical&amp;nbsp; address&amp;nbsp; 0xA0008000 is given to SDRAM Controller and controller in turn issue the Row address(A0 -A12) and column address(A0-A8) in the clock after tRAS. Refer the data sheet for all the timing.&lt;BR /&gt;&lt;BR /&gt;I beleive the above explanation helps you.&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;DIV&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 18 Jun 2008 23:21:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SDRAM-Address-testing/m-p/164402#M931</guid>
      <dc:creator>Rame</dc:creator>
      <dc:date>2008-06-18T23:21:29Z</dc:date>
    </item>
  </channel>
</rss>

