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    <title>Other NXP ProductsのトピックS32R274 Spinlock abnormal</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999505#M8373</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I use the instruction lwarx &amp;amp; stwcx. implement the Spinlock function on S32R274。&lt;/P&gt;&lt;P&gt;After a lot of test whitch between Z4 core and Z70 core，I found Spinlock fails sometimes。Z4 core and Z7 core enter the protect area at the same time。&lt;/P&gt;&lt;P&gt;Spinlock variable value is share sram data which attribute is uncacheable。&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 04 Dec 2019 02:15:39 GMT</pubDate>
    <dc:creator>yadi_zhang</dc:creator>
    <dc:date>2019-12-04T02:15:39Z</dc:date>
    <item>
      <title>S32R274 Spinlock abnormal</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999505#M8373</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I use the instruction lwarx &amp;amp; stwcx. implement the Spinlock function on S32R274。&lt;/P&gt;&lt;P&gt;After a lot of test whitch between Z4 core and Z70 core，I found Spinlock fails sometimes。Z4 core and Z7 core enter the protect area at the same time。&lt;/P&gt;&lt;P&gt;Spinlock variable value is share sram data which attribute is uncacheable。&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 04 Dec 2019 02:15:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999505#M8373</guid>
      <dc:creator>yadi_zhang</dc:creator>
      <dc:date>2019-12-04T02:15:39Z</dc:date>
    </item>
    <item>
      <title>Re: S32R274 Spinlock abnormal</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999506#M8374</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;this was already discussed here:&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" class="link-titled" href="https://community.nxp.com/thread/437523#comment-856994" title="https://community.nxp.com/thread/437523#comment-856994"&gt;https://community.nxp.com/thread/437523#comment-856994&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;None of MPC57xx devices (S32R274 also belongs here) have the reservation logic implemented between cores.&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm afraid the only option is to use semaphores (SEMA42 module).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Lukas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 09 Dec 2019 09:11:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999506#M8374</guid>
      <dc:creator>lukaszadrapa</dc:creator>
      <dc:date>2019-12-09T09:11:49Z</dc:date>
    </item>
    <item>
      <title>Re: S32R274 Spinlock abnormal</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999507#M8375</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lukas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I have seen your link，I thought S32R274 was different，but the result is not support，It‘s too bad.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Thank you for your support!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 10 Dec 2019 01:09:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/S32R274-Spinlock-abnormal/m-p/999507#M8375</guid>
      <dc:creator>yadi_zhang</dc:creator>
      <dc:date>2019-12-10T01:09:36Z</dc:date>
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