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    <title>topic SJA1105 RMII ref_clk configuration in Other NXP Products</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/987693#M8274</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have a board where a PHY is connected to a SJA1105Q switch via RMII. Other than descripbed in the switch reference manual, the 50MHz reference clock is generated by the PHY and supplied to the switch port's REF_CLK pin.&lt;/P&gt;&lt;P&gt;Is it possible to configure the REF_CLK pin to be an input when the switch port is in MAC mode?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Georg&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 19 Feb 2020 12:25:25 GMT</pubDate>
    <dc:creator>georgwaibel</dc:creator>
    <dc:date>2020-02-19T12:25:25Z</dc:date>
    <item>
      <title>SJA1105 RMII ref_clk configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/987693#M8274</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have a board where a PHY is connected to a SJA1105Q switch via RMII. Other than descripbed in the switch reference manual, the 50MHz reference clock is generated by the PHY and supplied to the switch port's REF_CLK pin.&lt;/P&gt;&lt;P&gt;Is it possible to configure the REF_CLK pin to be an input when the switch port is in MAC mode?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Georg&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 19 Feb 2020 12:25:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/987693#M8274</guid>
      <dc:creator>georgwaibel</dc:creator>
      <dc:date>2020-02-19T12:25:25Z</dc:date>
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    <item>
      <title>Re: SJA1105 RMII ref_clk configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/987694#M8275</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;No, it is not possible. In MAC mode RMII port of the switch outputs REF_CLK only. You can either, change configuration of the PHY to use external REF_CLK (from the switch), or set the switch's port to RMII PHY mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 20 Feb 2020 11:47:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/987694#M8275</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2020-02-20T11:47:48Z</dc:date>
    </item>
    <item>
      <title>Re: SJA1105 RMII ref_clk configuration</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/1757970#M20124</link>
      <description>&lt;P&gt;Hi,NXP experts，&lt;/P&gt;&lt;P&gt;There is a description in datasheet page15 like below.From my understanding the REF_CLK can be used as an output even acts as RMII MAC&amp;nbsp; mode.&lt;/P&gt;&lt;P&gt;Can you please explain more?Thank you.&lt;/P&gt;&lt;P&gt;"RMII data is exchanged via 2-bit data signals TXD[1:0] and RXD[1:0] as shown in&lt;BR /&gt;Figure 7. Transmit and receive signals are synchronized with the shared reference clock,&lt;BR /&gt;REF_CLK.&lt;BR /&gt;In both the PHY-MAC (i.e. PHY to switch) and MAC-MAC (i.e. processor to switch)&lt;BR /&gt;configurations, the REF_CLK output on the Ethernet switch can provide the shared&lt;BR /&gt;reference clock."&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Yang&lt;/P&gt;</description>
      <pubDate>Thu, 16 Nov 2023 01:55:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/SJA1105-RMII-ref-clk-configuration/m-p/1757970#M20124</guid>
      <dc:creator>Yangg</dc:creator>
      <dc:date>2023-11-16T01:55:22Z</dc:date>
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