topic Re: PCF2129 false timestamp on power fail in Other NXP Products

PCF2129 false timestamp on power fail

neilla — Tue, 29 Oct 2019 09:32:56 GMT

We are currently using a PCF2129 with the timestamp input being used for tamper detection. It is normally running with 3.3V supply for VDD with a 3.6V lithium battery as the backup supply, and is communicating using I2C. When power is removed, VDD drops with a rate of ~0.4V/ms and the battery switch over works as normal, it is running in the standard switch over mode. However on the next power up we are noticing that the TSF1 flag is set indicating an intermediate level timestamp, the TS input pin is connected to switches that are open so no timestamp should be seen.

Is there any reason for this behaviour?

Re: PCF2129 false timestamp on power fail

guoweisun — Fri, 01 Nov 2019 06:43:25 GMT

Could you please show your schematic?

Thanks!

Re: PCF2129 false timestamp on power fail

neilla — Fri, 08 Nov 2019 09:15:41 GMT

Hi,

Here is the schematic for the PCF2129, the TAMPER signal goes off to a microswitch, as does J14, pin 2 of J14 goes to a GPIO pin of another device to detect if the microswitch is actually connected to J14.

Re: PCF2129 false timestamp on power fail

guoweisun — Fri, 22 Nov 2019 02:44:53 GMT

So you select the standard mode abot Battery switch-over function,right?

Re: PCF2129 false timestamp on power fail

neilla — Fri, 22 Nov 2019 09:23:28 GMT

Yes, the battery switchover is running in the default standard mode.

Re: PCF2129 false timestamp on power fail

guoweisun — Mon, 25 Nov 2019 06:03:17 GMT

---

Please get note that :

When the TS input pin is driven to an intermediate level between the power supply

and ground, either on the falling edge from VDD or on the rising edge from ground,

then the following sequence occurs:

The actual date and time are stored in the timestamp registers.
The timestamp flag TSF1 (register Control_1) is set.
If the TSIE bit (register Control_2) is active, an interrupt on the INT pin is

generated.

The TSF1 flag can be cleared by command. Clearing the flag clears the interrupt.

Once TSF1 is cleared, it will only be set again when a new negative or positive edge

on pin TS is detected.

---

For the schematic update when using switches or push-buttons, it is recommended to connect a 1 nF capacitance to the TS
pin to ensure proper switching.

Re: PCF2129 false timestamp on power fail

ivekengineer — Mon, 06 Jul 2020 18:02:18 GMT

I'm discovering an issue on my board and I wonder whether is similar to the issue you are seeing. Into what type of device is the J14-pin 2 signal going, and is it's power supply domain different than VBAT? The TS signal is connected to VBAT internal to the PCF2129. When your 3.3V supply is powered own, the TS pin provides a current path to VBAT through the internal 200k resistor. If your device is on the 3.3V domain, and if it has a typical input with esd protection diodes, then one of them would turn on when the 3.3V supply is off. I suspect if you measured J12-pin 2 with the 3.3V supply off you would measure ~0.3-0.4V.

Besides causing a timestamp event, this issue would cause an additional current draw of ~16uA which could significantly reduce the hold-up time of your battery (3.6V-0.4V/200k = 16uA).

If this is the case, NXP really should provide some warning of this in either the app note or datasheet as I would suspect it is pretty common to interface the TS pin with a solid state device (i.e., non mechanical switch) to monitor the state of it.