Other NXP ProductsのトピックRe: SJA1124 clock input

SJA1124 clock input

Skaptor — Wed, 03 Apr 2019 20:21:31 GMT

Hello,

It's been a while since I've used this forum (apologies if this post is in the wrong place). I am interested in using an SJA1124 IC. I don't fully understand the "CLK" input. Am I supposed to use an external oscillator or use an mcu clock output?

I hope someone has already dealt with this

Regards.

Re: SJA1124 clock input

reyes — Thu, 04 Apr 2019 15:38:57 GMT

Hi JuanCar,

A good quality input clock is necessary for proper PLL performance. It can be either from an external oscillator or from a mcu clock output as long as the frequency of the reference clock on pin CLK is within the specified operating range, fclk(PLL)in. = External reference frequency operating range between 0.4 and 10 MHz.

To meet LIN master requirements for baud rate deviation, the tolerance of the external clock reference should be within ±0.3%.

Have a great day,
Jose

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Re: SJA1124 clock input

Skaptor — Thu, 04 Apr 2019 16:38:04 GMT

Hello Jose,

Thanks for the quick answer. So is it ok if I use an external 8MHz oscillator? Then the PLL can be adjusted from the registers so that I can generated any desired baudrate. is this right?

Re: SJA1124 clock input

reyes — Thu, 04 Apr 2019 20:28:03 GMT

Hi JuanCar,

Yes, it is ok if you use a 8MHz oscillator and the PLL can be adjusted from the registers so that you can generate any desired baudrate.

But it is important that the tolerance of the external clock reference should be within ±0.3%.

Re: SJA1124 clock input

Skaptor — Tue, 11 Jun 2019 18:32:49 GMT

Hello Jose,

The boards finally arrived, do you know where I can get some example code? I am having trouble getting the "LIN normal mode" status