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    <title>Other NXP ProductsのトピックRe: UJA1135 System Base Chip SPI Communication</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820149#M6321</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ashlie,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you have a logic analyzer or an oscilloscope to check if the timing and format of the SPI message is correct?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please note that the UJA1135 uses the “Mode 1” SPI protocol, which means that an inactive state of clock signal is low (CPOL = 0) and data are captured on the falling edge of clock signal and changed on the rising edge (CPHA = 1):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/68145i45958B8995A49710/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Also note that the 7-bit register address needs to be placed in the upper 7 bits of the first byte and the Read/Write bit is in the LSB:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/68094iA5D1C610D0279BC2/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For example, the 7-bit address of the Fail-safe control register (0x02) translates to 0x04 (0x02 &amp;lt;&amp;lt; 1) for a write and 0x05 ([0x02 &amp;lt;&amp;lt; 1] | 0x01) for a read.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Tomas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 27 Aug 2018 10:13:49 GMT</pubDate>
    <dc:creator>TomasVaverka</dc:creator>
    <dc:date>2018-08-27T10:13:49Z</dc:date>
    <item>
      <title>UJA1135 System Base Chip SPI Communication</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820148#M6320</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have met some questions about UJA1135 SBC’ SPI communication.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;1. When I tried to control MCU to read the contents of any selected register in SBC by SPI, the data returned was always 0. &lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;2. I want to configurate the LIMP pin into outputting the low level and the HVIO4 pin into the high level, so I write 0x02(address), 0x04(data) and 0x33(address),0x0D(data). And I know the LSB of the address should be 0 to indicate a write operation. However, these operations failed.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I wonder if there are someplace that I neglected or I did something wrong.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Aug 2018 02:26:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820148#M6320</guid>
      <dc:creator>Ashlie</dc:creator>
      <dc:date>2018-08-24T02:26:19Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1135 System Base Chip SPI Communication</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820149#M6321</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ashlie,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Do you have a logic analyzer or an oscilloscope to check if the timing and format of the SPI message is correct?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please note that the UJA1135 uses the “Mode 1” SPI protocol, which means that an inactive state of clock signal is low (CPOL = 0) and data are captured on the falling edge of clock signal and changed on the rising edge (CPHA = 1):&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_3.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/68145i45958B8995A49710/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_3.png" alt="pastedImage_3.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Also note that the 7-bit register address needs to be placed in the upper 7 bits of the first byte and the Read/Write bit is in the LSB:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/68094iA5D1C610D0279BC2/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For example, the 7-bit address of the Fail-safe control register (0x02) translates to 0x04 (0x02 &amp;lt;&amp;lt; 1) for a write and 0x05 ([0x02 &amp;lt;&amp;lt; 1] | 0x01) for a read.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I hope it helps.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Tomas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Aug 2018 10:13:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820149#M6321</guid>
      <dc:creator>TomasVaverka</dc:creator>
      <dc:date>2018-08-27T10:13:49Z</dc:date>
    </item>
    <item>
      <title>Re: UJA1135 System Base Chip SPI Communication</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820150#M6322</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Tomas,&lt;/P&gt;&lt;P&gt;Thanks for your reply. But I found the reason of my problem should be another one. That t&lt;SPAN class=""&gt;he factory preset values had been restored&lt;/SPAN&gt;&amp;nbsp;caused&amp;nbsp;&lt;SPAN class=""&gt;the SBC entered Forced Normal Mode. So the SPI communication was limited in the Forced Normal Mode.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Now I&amp;nbsp;hope to exit the Forced Normal Mode and let SBC work in the normal mode, so I&amp;nbsp;followed the data sheet. First, pin RSTN and pin CANL are pulled down to GND, and pin CANH is pulled up to 12V.&amp;nbsp; &lt;SPAN class=""&gt;After the factory preset values have been restored, I download the program with MTPNV to MCU(I want to disable the bit FNMC) while the SBC not power-off. Next I make MCU and SBC power-off and then MCU power-on. Finally I read bit&amp;nbsp; FNMC and some other bits find that SBC is still in Forced Normal Mode.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I wonder what's wrong with my methods and&amp;nbsp; a new SBC works in normal mode or forced normal mode.&lt;BR style="font-weight: normal;" /&gt; &lt;BR style="font-weight: normal;" /&gt; Best regards,&lt;/P&gt;&lt;P&gt;Ashlie&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 04:29:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/UJA1135-System-Base-Chip-SPI-Communication/m-p/820150#M6322</guid>
      <dc:creator>Ashlie</dc:creator>
      <dc:date>2018-08-29T04:29:17Z</dc:date>
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