<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Other NXP ProductsのトピックMPC8313 DDR2 Using 2 ddr2s 14X10X3 on single chip select?</title>
    <link>https://community.nxp.com/t5/Other-NXP-Products/MPC8313-DDR2-Using-2-ddr2s-14X10X3-on-single-chip-select/m-p/667765#M4682</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have 2 128MBitsX16 (14X10X3) on a single Chip Select. &amp;nbsp; We can address 0-256 MByte &amp;nbsp;but not 256MByte to 512Mbyte? &amp;nbsp;We have cs_bnds, cs_config, and &amp;nbsp;ddrlaw[0] set correctly I believe. &amp;nbsp; 8313 docs show (Table 9-26) shows this as a valid supported device. &amp;nbsp;However Table 9.30 does not show 14X10X3 as an option. &amp;nbsp; Can we run a 14X10X3 with a single Chip Select?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 20 Jun 2017 20:49:44 GMT</pubDate>
    <dc:creator>waynebush</dc:creator>
    <dc:date>2017-06-20T20:49:44Z</dc:date>
    <item>
      <title>MPC8313 DDR2 Using 2 ddr2s 14X10X3 on single chip select?</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/MPC8313-DDR2-Using-2-ddr2s-14X10X3-on-single-chip-select/m-p/667765#M4682</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We have 2 128MBitsX16 (14X10X3) on a single Chip Select. &amp;nbsp; We can address 0-256 MByte &amp;nbsp;but not 256MByte to 512Mbyte? &amp;nbsp;We have cs_bnds, cs_config, and &amp;nbsp;ddrlaw[0] set correctly I believe. &amp;nbsp; 8313 docs show (Table 9-26) shows this as a valid supported device. &amp;nbsp;However Table 9.30 does not show 14X10X3 as an option. &amp;nbsp; Can we run a 14X10X3 with a single Chip Select?&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Jun 2017 20:49:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/MPC8313-DDR2-Using-2-ddr2s-14X10X3-on-single-chip-select/m-p/667765#M4682</guid>
      <dc:creator>waynebush</dc:creator>
      <dc:date>2017-06-20T20:49:44Z</dc:date>
    </item>
    <item>
      <title>Re: MPC8313 DDR2 Using 2 ddr2s 14X10X3 on single chip select?</title>
      <link>https://community.nxp.com/t5/Other-NXP-Products/MPC8313-DDR2-Using-2-ddr2s-14X10X3-on-single-chip-select/m-p/667766#M4683</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/23593iBCF679DC01E4E30B/image-size/large?v=v2&amp;amp;px=999" title="8313snip.png" alt="8313snip.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/23639iC8CC3B83A88AB46B/image-size/large?v=v2&amp;amp;px=999" title="8313snap2.png" alt="8313snap2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Table 9-30 shows no support for 14X10X3 for 2-&amp;gt;128MbitX16 devices for 32-Bit DataBus&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 20 Jun 2017 21:09:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Other-NXP-Products/MPC8313-DDR2-Using-2-ddr2s-14X10X3-on-single-chip-select/m-p/667766#M4683</guid>
      <dc:creator>waynebush</dc:creator>
      <dc:date>2017-06-20T21:09:52Z</dc:date>
    </item>
  </channel>
</rss>

