topic Re: SGTL5000 Audio codec in Other NXP Products

SGTL5000 Audio codec

athulpavithran — Thu, 14 Jul 2016 16:41:52 GMT

I am inviting person got experience on audio codec to join.I am currently working with sgtl5000 ic. I configured its register with i2c, But after making use of internal PLL , i2c found to be not working. What can be the reason?

Re: SGTL5000 Audio codec

reyes — Wed, 20 Jul 2016 21:48:31 GMT

Hi Athul Pavithran,

I’m a Hardware engineer that has been working with the SGTL5000, I may help with the issue you are seeing.

The issue seems to be related to a problem with the initialization or configuration of the PLL, or an incompatibility of the clock ranges between the ones that you are trying to use and the ones that the SGTL5000 can handle.

I would recommend you to take a look at the following initialization/configuration settings steps required to use the internal PLL:

// Power up the PLL

Modify CHIP_ANA_POWER->PLL_POWERUP 0x0001 // bit 10

Modify CHIP_ANA_POWER->VCOAMP_POWERUP 0x0001 // bit 8

// NOTE: This step is required only when the external SYS_MCLK

// is above 17MHz. In this case the external SYS_MCLK clock

// must be divided by 2

Modify CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 0x0001 // bit 3

Sys_MCLK_Input_Freq = Sys_MCLK_Input_Freq/2;

// PLL output frequency is different based on the sample clock rate used.

if (Sys_Fs_Rate == 44.1kHz) PLL_Output_Freq = 180.6336MHz

else

PLL_Output_Freq = 196.608MHz

// Set the PLL dividers

Int_Divisor = floor(PLL_Output_Freq/Sys_MCLK_Input_Freq)

Frac_Divisor = ((PLL_Output_Freq/Sys_MCLK_Input_Freq) - Int_Divisor)*2048

Modify CHIP_PLL_CTRL->INT_DIVISOR Int_Divisor // bits 15:11

Modify CHIP_PLL_CTRL->FRAC_DIVISOR Frac_Divisor // bits 10:0

I hope this can help.

Have a great day,
Jose

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Re: SGTL5000 Audio codec

athulpavithran — Thu, 21 Jul 2016 14:50:17 GMT

Hello.... Jose Alberto,

Thank you for the replay and guidance.It helped me, Problem has solved. I didn't configure

"Modify CHIP_ANA_POWER->VCOAMP_POWERUP 0x0001 // bit 8 " this register bit that found to be the problem.Thank you.

Now I am trying to bypass the LINE_IN to HeadPhone_OUT, Unfortunately it doesn't work for the first attempt.

The register configuration i followed after PLL configuration is listed bellow.

CHIP_ANA_CTRL->SELECT_HP // set bit 6 route line_in to HP_OUT

write CHIP_ANA_HP_CTRL 0X7F7F

modify CHIP_ANA_CTRL ->MUTE_HP //4th bit to zero

is it fine? I am confused with the ground. Is it ok if both analog and digital ground common ?does the pad ground effects its working in any way(i didn't give ground to the pad). I given audio out of an mp3 module as an input to the LINE_IN ,where I can find analog signal in CRO while music is playing.but there is no effect at HP_OUT(headphone out),HP_GND has taken as reference ground.(mp3 module's ground and sgtl ground are made common).I am anticipating your constant support to make it success.

Thank you.

Re: SGTL5000 Audio codec

reyes — Fri, 22 Jul 2016 20:46:48 GMT

Hi Athul,

Glad to know that my comments helped you to solve your first problem.

Now, about how to route the signal from LINEIN to HP, the only configuration needed is as follow:

// Select LINEIN as the input to HP_OUT

Modify CHIP_ANA_CTRL->SELECT_HP 0x0001 // bit 6

About your question regarding the grounds, a proper grounds configuration is critical for audio signals, here are some recommendation around how to properly set the ground configuration for the SGTL5000:

Separate Analog Ground from Digital Ground.
Central Pad of the SGTL5000 must be soldered to ground.
AGND (pin 7) should be "star" connected to the jack grounds for LINEIN and LINEOUT, and to the VAG capacitor ground. This node should via to the ground plane (or connected to ground) at a single point.

Star the ground pins of the chip, VAG ground, and all analog inputs/outputs to a single point, then to the ground plane.

HP_VGND pin stand for virtual ground. HP_VGND pin has a DC voltage hence it should never be instead of the GND_AUDIO (0V voltage), so leave HP_VGND open if SGTL5000 Headphone AC Mode is applied, it should never be connected to ground.

Have a great day,
Jose

Re: SGTL5000 Audio codec

athulpavithran — Sat, 30 Jul 2016 16:42:05 GMT

Yes, It had happened.Bypassing the signal from line_in to headphone_out was accomplished.Now it is a turn to do the i2s. I am doing it with the application processor LPC1768. I did a trail to receive the data without DMA control and rx_fifo buffer was read continuously. I can find a changes in the buffer on data transmission.I will feel easy if i get to know the data manipulation mechanism in i2s with dma.

Re: SGTL5000 Audio codec

athulpavithran — Sat, 30 Jul 2016 16:46:50 GMT

Bypassing was accomplished.please find the next comment,I think you can help me.

Thank You.

Re: SGTL5000 Audio codec

reyes — Mon, 01 Aug 2016 17:09:42 GMT

Hi Athul,

You can find an example about the data manipulation mechanism in I2S + DMA in the application note AN11178 “MP3 player solution on NXP LPC1700 series” by downloading the .zip file from the following link: http://www.nxp.com/documents/application_note/AN11178.zip

Have a great day,
Jose

Re: SGTL5000 Audio codec

athulpavithran — Thu, 18 Aug 2016 03:23:05 GMT

Hi Jose Alberto,

I am little confused over i2s 4-line, That is the SGTL5000 has got four i2s pins 1)DOUT 2)DIN 3)SCK 4)WS where as lpc4357(currently using processor) found to be eight pins 1)RX_SDA 2)TX_SDA 3)RX_SCK 4)TX_SCK 5) RX_WS 6)TX_WS 7)RX_ MCLK 8)TX_MCLK. I am not understanding the purpose of RX_MCLK and TX_MCLK. How do i interface sgtl5000 4-line i2s with lpc4357 3-line i2s(separate for RX and TX) ?. Looking for your replay.

Thank you.

Re: SGTL5000 Audio codec

reyes — Wed, 24 Aug 2016 19:39:32 GMT

Hi Athul,

Sorry for the delay in my answer.

This is how you can connect the LPC4357 with the SGTL5000 I2S lines:

SGTL5000_DOUT to LPC4357_RX_SDA

SGTL5000_DIN to LPC4357_TX_SDA

SGTL5000_SCK to LPC4357_RX_SCK

SGTL5000_WS to LPC4357_RX_WS

Have a great day,
Jose

Re: SGTL5000 Audio codec

athulpavithran — Fri, 26 Aug 2016 15:58:42 GMT

Thank you jose,

In my application ,the processor should do transmit as well receive.I think it should follow i2s 3-line mode for reception and i2s 4-line mode for transmission. isn't it so?.I have decided to fix the lpc4357 as i2s master with RX_MCLK (master clock) out and codec SGTL5000 as slave(Master clock RX_MCLk =12.28mhz as system clock for sgtl5000). is it all fine or do i need any diversion? Waiting for your replay.

Re: SGTL5000 Audio codec

reyes — Mon, 29 Aug 2016 13:48:42 GMT

Hi Athul,

Seems correct, I don't think that you need any diversion.

-Jose

Re: SGTL5000 Audio codec

athulpavithran — Sat, 15 Oct 2016 05:04:39 GMT

Hlo...

I was little busy with other work. Currently I fixed all hardware issues and seems to be ready to work. I given a dummy data like 0x02356755 through i2s and routed it to headphone out via DAC. A sound like "keeee" was noticed and changing the data also changes the output.Can you provide me a valid audible data to test sgtl5000?

Thank You.