Cascading 74LVC595A shift registers

franzforstmayr — Mon, 01 Aug 2016 09:10:50 GMT

Hey,
the 74LVC595A shift registers reads the incoming data with the rising clock edge. The serial data output is also clocked on the rising edge of the SHCP. Could there be a problem when cascading several 74LVC595A devices, due to propagation delay and hold time? I mean the cascaded register has a hold time of minimum 1.5ns at 3.3V, the data output could have a propagation delay of 1.5ns. This means the second register can see a changing input pin 1.5ns after the clock pulse, so layout effects of a few ps can make my device unfunctional by reading strange things.

Is there a good way to avoid problems like this? Why isn't a additional Q7S flip flop in the device, which latches the data out at the falling clock edge?

Yours Franz

Re: Cascading 74LVC595A shift registers

Bulat — Wed, 03 Aug 2016 12:16:24 GMT

It should not be a problem, everything will work correctly as you expect.
If you are going to work at very high clock frequencies, there is a reason to pay attention to clock routing. Specifically, clock delay from the clock source to clock inputs of all shift registers should be the same.

Regards,

Bulat

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Cascading 74LVC595A shift registers

Re: Cascading 74LVC595A shift registers