TJA1120A RGMII Mode- Delay Config

vikyhre — Wed, 22 Jul 2026 08:23:39 GMT

This is the Device-Tree for TJA1120A - cpsw_port1, cpsw3g_phy0

&cpsw_port1 { status = "okay"; phy-mode = "rgmii-txid"; phy-handle = <&cpsw3g_phy0>; }; &cpsw_port2 { status = "okay"; phy-mode = "rgmii"; phy-handle = <&cpsw3g_phy1>; }; &cpsw3g_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; cpsw3g_phy0: ethernet-phy@0 { compatible = "ethernet-phy-id001b.b031"; reg = <4>; }; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id0022.1620"; reg = <0>; txc-skew-ps = <900>; rxc-skew-ps = <900>; rxd0-skew-ps = <420>; rxd1-skew-ps = <420>; rxd2-skew-ps = <420>; rxd3-skew-ps = <420>; txd0-skew-ps = <420>; txd1-skew-ps = <420>; txd2-skew-ps = <420>; txd3-skew-ps = <420>; rxdv-skew-ps = <420>; txen-skew-ps = <420>; }; };

Here we give "rgmii-txid" as phy-mode for TJA1120A.

But when I read register RGMII_TXC_DELAY_CONFIG, it reads 0x0014 which means no delay(15th bit), and RGMII_RXC_DELAY_CONFIG reads 0x8014 with means delay is set(15th bit).

Also if i change phy-mode to "rgmii-rxid" in DT, RGMII_RXC_DELAY_CONFIG reads 0x0014, and RGMII_TXC_DELAY_CONFIG reads 0x8014.

I just tried setting "rgmii" in DT and then setting these registers using phytool, it had reflected perfectly and started pinging then RGMII_RXC_DELAY_CONFIG 15th bit set to HIGH and RGMII_TXC_DELAY_CONFIG 15th bit set to LOW.

I wish to understand why this reversal happen at DT configuration of phy-mode.

For our AM62A7 based ECU, internal delay on RX_Clock is needed by PCB, so it set "rgmii-txid". Its working perfectly fine.

Also I would like to know the use of Pin Strapping for this PHY-Mode, if DTS takes care of it.

Re: TJA1120A RGMII Mode- Delay Config

PetrS — Thu, 23 Jul 2026 08:16:11 GMT

Hi,

Based on the TJA1120A documentation, the RGMII delay configuration can be a bit confusing because the register names and the delay described inside the register do not directly match.

Please refer to the RGMII_RXC_DELAY_CONFIG/RGMII_TXC_DELAY_CONFIG registers bit description within device DS:

0xAFCC RGMII_RXC_DELAY_CONFIG: bit 15 = enables internal TXC delay
0xAFCD RGMII_TXC_DELAY_CONFIG: bit 15 = enables internal RXC delay
 

So, when checking the configuration, the important point is the actual register bit description and the final register read-back value after initialization.

Also note that pin strapping only defines the default configuration after reset. The software driver can overwrite this later via MDIO, so the effective configuration should be verified by reading back the registers after the system has booted.

Please also make sure that the same RGMII clock delay is not enabled on both MAC and PHY side unless this is intended by the board timing design.

BR, Petr

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