topic Re: Backplane RapidIO communication between two MPC8641d based Custom Boards in Other NXP Products

Backplane RapidIO communication between two MPC8641d based Custom Boards

ashishkhetan — Tue, 05 May 2015 14:45:03 GMT

@Hi,

I have been facing a strange issue in linux while probing for the srio devices. In current configuration there are two boards connected through backplane in 4x mode. Neither of the board is detecting srio link. I am using Linux OS (Linux-3.14). Here I am putting some booting message that has been captured while booting for rapid IO, that might help to understand the problem

The following output is from Board 1

pci 0000:00:00.0: bridge window [mem 0x80000000-0x9fffffff]

Setting up RapidIO peer-to-peer network /rapidio@D00c0000

fsl-of-rio d00c0000.rapidio: Of-device full name /rapidio@D00c0000

fsl-of-rio d00c0000.rapidio: Regs: [mem 0xd00c0000-0xd00dffff]

fsl-of-rio d00c0000.rapidio: bellirq: 0

fsl-of-rio d00c0000.rapidio: pwirq: 0

fsl-of-rio d00c0000.rapidio: Can't get /rapidio@D00c0000/port1 property 'ranges'

fsl-of-rio: probe of d00c0000.rapidio failed with error -67

bio: create slab <bio-0> at 0

The following output from Board 2:

pci 0000:00:00.0: bridge window [mem 0x80000000-0x9fffffff]

Setting up RapidIO peer-to-peer network /rapidio@D00c0000

fsl-of-rio d00c0000.rapidio: Of-device full name /rapidio@D00c0000

fsl-of-rio d00c0000.rapidio: Regs: [mem 0xd00c0000-0xd00dffff]

fsl-of-rio d00c0000.rapidio: bellirq: 0

fsl-of-rio d00c0000.rapidio: pwirq: 0

fsl-of-rio d00c0000.rapidio: Can't get /rapidio@D00c0000/port1 property 'ranges'

fsl-of-rio: probe of d00c0000.rapidio failed with error -67

bio: create slab <bio-0> at 0

Freescale Elo series DMA driver

Both Boards are connected in host mode with different ID. Here I am putting device tree snapshot for rapid IO:

rapidio: rapidio@D00c0000 {

#address-cells = <2>;

#size-cells = <2>;

compatible = "fsl,srio";

reg = <0xD00c0000 0x20000>;

ranges = <0x0 0x0 0xb0000000 0x0 0x10000000>;

interrupt-parent = <&mpic>;

interrupts = <48 2>;

fsl,srio-rmu-handle = <&rmu>;

}

Please suggest some pointers/tips, that will be really helpfull.

and Thanks in Advance.

Regards

@$HI$H

Re: Backplane RapidIO communication between two MPC8641d based Custom Boards

ufedor — Fri, 08 May 2015 02:40:14 GMT

Please ensure that the link has been established - i.e. ESCSR[PO]=1

Re: Backplane RapidIO communication between two MPC8641d based Custom Boards

ashishkhetan — Fri, 15 May 2015 07:29:03 GMT

Thanks for Your Reply...

The link has not been established - i.e. ESCSR[PO]=0.

Here are the updates :

Board 1

fsl-of-rio d00c0000.rapidio: Port 0 is not ready. Try to restart connection...

fsl-of-rio d00c0000.rapidio: Port 0 restart failed.

fsl-of-rio d00c0000.rapidio: Port 0 is not ready. Try to restart connection...

fsl-of-rio d00c0000.rapidio: Port 0 restart failed.

fsl-of-rio d00c0000.rapidio: Port 0 is not ready. Try to restart connection...

fsl-of-rio d00c0000.rapidio: Port 0 restart failed.

fsl-of-rio d00c0000.rapidio: Port 0 is not ready. Try to restart connection...

fsl-of-rio d00c0000.rapidio: Port 0 restart failed.

fsl-of-rio d00c0000.rapidio: Port 0 restart success!

fsl-of-rio d00c0000.rapidio: Hardware port width: 1

fsl-of-rio d00c0000.rapidio: Training connection status: Single-lane 0

fsl-of-rio d00c0000.rapidio: RapidIO Common Transport System size: 256

/soc8641@d0000000/rmu@d3000/message-unit@0: txirq: 53, rxirq 54

Board 2

fsl-of-rio d00c0000.rapidio: Port 0 is not ready. Try to restart connection...

fsl-of-rio d00c0000.rapidio: Port 0 restart success!

fsl-of-rio d00c0000.rapidio: Hardware port width: 1

fsl-of-rio d00c0000.rapidio: Training connection status: Single-lane 0

fsl-of-rio d00c0000.rapidio: RapidIO Common Transport System size: 256

/soc8641@d0000000/rmu@d3000/message-unit@0: txirq: 53, rxirq 54

RIO: enumerate master port 0, RIO mport 0
fsl_local_config_write: index 0 offset 00000068 data 00000000
fsl_local_config_read: index 0 window=f1040000 offset 68 data=0
fsl_local_config_write: index 0 offset 00000060 data 00000000
fsl_local_config_read: index 0 window=f1040000 offset c data=100
fsl_local_config_read: index 0 window=f1040000 offset 100 data=6000001
fsl_local_config_read: index 0 window=f1040000 offset 158 data=30301
RIO: master port 0 link inactive

Can you Please suggest any thing...

Re: Backplane RapidIO communication between two MPC8641d based Custom Boards

marek_neuzil — Tue, 09 Jun 2015 12:24:53 GMT

Hello Ashish,

The MPC8641s is a Power Architecture Processor. Your question should be answered in the Other Freescale Solutions space (see High-performance Dual Core Processor|Freescale ). I am moving this discussion thread into this space. The Processor Expert Software space is dedicated for Processor Expert products.

You can also look into this space if there are the same or similar issues resolved.

Best Regards,

Marek Neuzil