Requesting eRPC over SPI official data, benchmarks, or references

sg_TP — Wed, 13 May 2026 12:30:56 GMT

Hi NXP Team,

I am working on an implementation of Zephyr eRPC over SPI between two MCUs and would like to understand the performance characteristics of this setup.

I am looking for any official data, benchmarks, or references related to the following:

Throughput (TX and RX) achievable over SPI using eRPC
Latency or round trip time for RPC calls
Impact of payload size such as 256B, 512B, 1KB, 2KB and above on performance
Effect of serialization and deserialization overhead
Recommended SPI clock frequencies for optimal performance
CPU load or RTOS overhead if measured
Differences in performance between Zephyr-based implementations and MCUXpresso SDK native implementations

I am particularly interested in any reference designs or example projects demonstrating eRPC over SPI, and any measured benchmarks on NXP platforms such as i.MX RT or LPC.

Thanks in advance for your support.

Best regards,

Re: Requesting eRPC over SPI official data, benchmarks, or references

mayliu1 — Mon, 25 May 2026 06:31:17 GMT

Hi @sg_TP ,

Thank you so much for your interest in our products and for using our community.

I have reviewed the available documentation and did not find any official NXP material that provides quantified performance benchmarks for eRPC over SPI (for example, throughput, latency/round-trip time, or CPU load).

Please note that eRPC is not equivalent to raw SPI transport performance. As a higher-layer RPC framework running on top of SPI, its overall performance is influenced by additional factors such as serialization/deserialization, protocol framing, synchronization, and software scheduling.

In practical designs, eRPC communication over SPI is also not just a simple SPI data transfer. It typically requires one or two additional GPIO signals for handshake or data-ready synchronization to ensure proper coordination between the two MCU.

In addition, performance can vary significantly depending on the platform (for example, i.MX RT, LPC, MCX), as well as system-level factors such as CPU performance, cache, SPI+DMA capability, memory architecture, and application characteristics (payload size, call frequency, buffering strategy...).

As a practical approach, I recommend first evaluating the baseline SPI performance using SPI + DMA examples from MCUXpresso SDK or Zephyr SPI samples. Based on that baseline, the eRPC layer can then be added to assess the additional protocol overhead.

Best regards,

May

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Requesting eRPC over SPI official data, benchmarks, or references

Re: Requesting eRPC over SPI official data, benchmarks, or references