Other NXP Productsのトピックe200z0 (MPC560xB) Divider Logic Performance

e200z0 (MPC560xB) Divider Logic Performance

mahi — Mon, 01 Dec 2014 10:53:12 GMT

Hello Community,

the MPC560xB reference manual describes the e200 integer unit's features like that:

• Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution timing

• 8x32 hardware multiplier array supports 1 to 4 cycle 32x32->32 multiply

The e200z0 reference manual says the timing is "data dependent".

Is there a document (I didn't see yet) giving more information (e.g. a table with the different div and mul instructions with timings)?

Best Regards,

Martin

Re: e200z0 (MPC560xB) Divider Logic Performance

davidtosenovjan — Tue, 02 Dec 2014 13:07:21 GMT

I am afraid there is no such document (at least not for public).

“Divide instructions have a latency of 5–34 cycles depending on the operand data. While the divide is running, the rest of the pipeline is unavailable for additional instructions (blocking divide).”

Let’s imagine you manually divide numbers on the paper. It takes variable number of lines according to operands until you reach indivisible remainder. MCU’s divider works the similar way.

If you do some performance analysis, you should count with worst-case, thus 34 cycles.