Other NXP ProductsのトピックRe: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

LedHx — Wed, 29 Apr 2026 01:44:14 GMT

Hello,

I am using the LS1028A evaluation board. I followed the documentation and built the boot image for the LS1028A using the command bld -m ls1028ardb. After flashing the image to an SD card and booting the system, I am unable to configure eno0 within the system. The error is as follows:

root@ls1028ardb:~# ifconfig eno0 192.168.0.110 [ 312.156125] net eno0: could not attach to PHY SIOCSIFFLAGS: No such device

Upon checking the logs, I found the following error:

fsl_enetc_mdio 0000:00:00.3: probe with driver fsl_enetc_mdio failed with error -5

The log indicates that the MDIO driver failed to probe, preventing PHY attachment. Additionally, the log shows PHY connection timeouts not only for eneth but also for all four switch ports.

I used an oscilloscope to capture the signal levels on the EMI1_MDIO and EMI1_MDC pins. EMI1_MDC continuously outputs a square wave at 670 kHz, which appears normal. However, the EMI1_MDIO pin remains high at all times when using the mdio command in U-Boot to query the PHY ID. The U-Boot commands and their outputs are shown below:

=> mdio list enetc-0: emdio-3: 2 - AR8031/AR8033 <--> enetc-0 10 - Generic PHY <--> swp0 11 - Generic PHY <--> swp1 12 - Generic PHY <--> swp2 13 - Generic PHY <--> swp3 enetc-2: felix-switch: => => mdio read enetc-2 2 0x02 Reading from bus enetc-2 PHY at address 2: 2 - 0x83 => mdio read enetc-2 2 0x03 Reading from bus enetc-2 PHY at address 2: 3 - 0xe400 => mdio read enetc-0 2 0x02 Reading from bus enetc-0 PHY at address 2: 2 - 0x0 => mdio read enetc-0 2 0x03 Reading from bus enetc-0 PHY at address 2: 3 - 0x0 => mdio read emdio-3 2 0x00 Reading from bus emdio-3 PHY at address 2: TT0 - 0x9200 => mdio read emdio-3 2 0x02 Reading from bus emdio-3 PHY at address 2: TT2 - 0x9200 => mdio read emdio-3 2 0x03 Reading from bus emdio-3 PHY at address 2: TT3 - 0x9200 =>

I suspect the issue lies in this area. However, I have thoroughly checked the RCW, device tree, and hardware, but have not found any obvious errors. Below is the timeout log from the boot process:

NOTICE: Fixed DDR on board NOTICE: 4 GB DDR4, 32-bit, CL=11, ECC on NOTICE: BL2: v2.12.0(release):lf-6.12.20-2.0.0 NOTICE: BL2: Built : 14:45:11, Dec 4 2025 NOTICE: BL2: Booting BL31 NOTICE: BL31: v2.12.0(release):lf-6.12.20-2.0.0 NOTICE: BL31: Built : 14:45:14, Dec 4 2025 NOTICE: Welcome to ls1028ardb BL31 Phase U-Boot 2025.04 (Dec 04 2025 - 14:45:02 +0800) SoC: LS1028A Rev1.0 (0x870b0110) Clock Configuration: CPU0(A72):1500 MHz CPU1(A72):1500 MHz Bus: 400 MHz DDR: 1600 MT/s Reset Configuration Word (RCW): 00000000: 3c004010 00000030 00000000 00000000 00000010: 00000000 018f0000 0030c000 00000000 00000020: 020031a0 00002580 00000000 00003296 00000030: 00000000 00000010 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 200e705a 00000000 00000070: bb580000 00000000 Model: LS1028A RDB Board Board: LS1028A Rev1.0-RDB, Version: C, boot from SD FPGA: v8 (RDB) SERDES1 Reference : Clock1 = 100.00MHz Clock2 = 100.00MHz DRAM: 3.9 GiB DDR 3.9 GiB (DDR4, 32-bit, CL=11, ECC on) Using SERDES1 Protocol: 47960 (0xbb58) PCIe1: pcie@3400000 Root Complex: no link PCIe2: pcie@3500000 Root Complex: no link Core: 58 devices, 26 uclasses, devicetree: separate WDT: Started watchdog@c000000 with servicing every 1000ms (60s timeout) WDT: Started watchdog@c010000 with servicing every 1000ms (60s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... Reading from MMC(0)... *** Warning - bad CRC, using default environment EEPROM: Invalid ID (ff ff ff ff) In: serial Out: serial Err: serial SEC0: RNG instantiated Net: TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT Warning: enetc-0 (eth0) using random MAC address - 3a:b9:c4:9e:93:20 eth0: enetc-0 Warning: enetc-2 (eth1) using random MAC address - 62:d9:2b:9d:bd:a5 , eth1: enetc-2TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth2: swp0TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth3: swp1TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth4: swp2TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTPHY reset timed out TTTTTTTTTTTTT, eth5: swp3

Could you please help identify possible causes for these issues?

Thank you.

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

yipingwang — Wed, 29 Apr 2026 05:29:23 GMT

Please check whether you can ping outside in u-boot through eno0?

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

LedHx — Wed, 29 Apr 2026 05:54:09 GMT

I also can't ping the PC from within U-Boot.In addition, I'd like to know if the output frequency of EMI1_MDC is 670 kHz? Our hardware engineer wants me to confirm this.

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

yipingwang — Wed, 29 Apr 2026 07:31:51 GMT

Please download LSDK 21.08 pre-build image as the following.

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/firmware_ls1028ardb_sdboot.img

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/boot_LS_arm64_lts_5.10.tgz
$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/rootfs_lsdk2108_ubuntu_main_arm64.tgz

Then deploy them to SD card.

$ wget https://www.nxp.com/lgfiles/sdk/lsdk2108/flex-installer && chmod +x flex-installer && sudo mv flex-installer /usr/bin

$ flex-installer -i pf -d /dev/sdb

$ flex-installer -f firmware_ls1028ardb_sdboot.img -b boot_LS_arm64_lts_5.10.tgz -r rootfs_lsdk2108_ubuntu_main_arm64.tgz -d /dev/sdb

Note:/dev/sdb is SD device name on your PC.

Then plugin SD card to the target board and configure LS1028ARDB switch setting as the following to configure the target board to boot from SD card.

Boot source SW2[1:8] SW3[1:8] SW5[1:8]
SD Card (SDHC1) 1000_1000 1111_0000 0011_1001

Boot to Linux from SD card and use "ethtool" to check the link status.

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

LedHx — Wed, 29 Apr 2026 09:55:46 GMT

I still can't configure eno0. The EMI1_MDIO pin remains constantly held high. Could you check from this log file whether the U-Boot and kernel boot processes are normal, respectively? Also, do the three files you provided boot normally on your development board? If they boot normally, is it possible that there is a hardware issue on my side? If there is a problem, can it be identified through the log?

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

yipingwang — Wed, 29 Apr 2026 10:07:14 GMT

Please follow my above procedure to deploy SD card and boot Ubuntu rootfs from SD card.

There is "ethtool" command in Ubuntu rootfs.

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

LedHx — Wed, 29 Apr 2026 13:44:00 GMT

The log file I provided above was configured exactly according to the procedure you gave. For details, please see my screenshot below.

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

LedHx — Thu, 30 Apr 2026 08:05:14 GMT

Previously, I didn't switch the flex-installer tool back to version 2108. Now I have completely followed your instructions to flash and boot the Ubuntu system. However, the eno0 network card is still not recognized. Our hardware is a custom board made according to the document "spf-39071_a1.pdf". The PHY chip corresponding to the eno0 network card has been replaced from AR8033 to AR8031, and the program flashed onto the CPLD chip is version v8.

Therefore, I have the following questions:

After replacing AR8033 with AR8031, is it fully compatible, and does the software need to be modified?
Will the version of the program flashed onto the CPLD chip affect the reset of the PHY chip?
Can the program you provided be adapted to this development board and correctly recognize the network cards?

The log is attached below. Looking forward to your reply.

Re: Why Cannot eno0 Be Configured and Why Is There No Signal Level Change on the MDIO Signal Pin?

yipingwang — Thu, 30 Apr 2026 08:40:40 GMT

In dts file arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts, please do the following modification according to the comments.

&enetc_mdio_pf3 {

sgmii_phy0: ethernet-phy@2 {

reg = <0x2>;// please modify the PHY address with enetc0 real PHY address on your custom board.

};

/* VSC8514 QSGMII quad PHY */

qsgmii_phy0: ethernet-phy@10 {

reg = <0x10>; // please modify the PHY address with swp0 real PHY address on your custom board.

};

qsgmii_phy1: ethernet-phy@11 {

reg = <0x11>;// please modify the PHY address with swp1 real PHY address on your custom board.

};

qsgmii_phy2: ethernet-phy@12 {

reg = <0x12>;// please modify the PHY address with swp2 real PHY address on your custom board.

};

qsgmii_phy3: ethernet-phy@13 {

reg = <0x13>; // please modify the PHY address with swp3 real PHY address on your custom board.

};